LTC3618_15 Datasheet, PDF(16/24 Page) Linear Technology – Dual 4MHz, 3A Synchronous Buck Converter for DDR Termination

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LTC3618_15 Datasheet, PDF (16/24 Pages) Linear Technology – Dual 4MHz, 3A Synchronous Buck Converter for DDR Termination

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LTC3618

Applications Information

Output Voltage Programming

The output voltage of VDDQ is set by external resistive

dividers. For example, VDDQ can be set according to the

following equation:

VDDQ = 0.6V â¢

1+ R1

The resistive divider allows pin VFB1 to sense a fraction

of the output voltage as shown in Figure 3.

Pulse-Skipping Mode

VDDQ pulse-skipping mode, which is a compromise

between low output voltage ripple and efficiency, can be

implemented by connecting the MODE/SYNC pin to SVIN.

In this condition, the peak inductor current is limited by

the minimum on-time of the current comparator. The low-

est output voltage ripple is achieved while still operating

discontinuously. During very light output loads, pulse-

skipping allows only a few switching cycles to skip while

maintaining the output voltage in regulation.

Internal and External Compensation

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC load current.

When a load step occurs, like the one shown in Figure 5,

VOUT shifts by an amount equal to âILOAD â¢ ESR, where

ESR is the effective series resistance of COUT. âILOAD

also begins to charge or discharge COUT, generating the

VOUT

200mV/DIV

1A/DIV

feedback error signal that forces the regulator to adapt

to the current change and return VOUT to its steady-state

value. During this recovery time, VOUT can be monitored

for excessive overshoot or ringing, which would indicate

a stability problem. The availability of the ITH pin allows

the transient response to be optimized over a wide range

of output capacitance.

The ITH1 external components (15.8k and 470pF) shown

in Figureâ¯3 will provide an adequate compensation as

well as a starting point for most applications. The values

can be modified slightly to optimize transient response

once the final PCB layout is complete and the particular

output capacitor type and value have been determined.

The output capacitors need to be selected because the

various types and values determine the loop gain and

phase. The gain of the loop will be increased by increas-

ing RC and the bandwidth of the loop will be increased

by decreasing CC. If RC is increased by the same factor

that CC is decreased, the zero frequency will be kept the

same, thereby keeping the phase shift the same in the

most critical frequency range of the feedback loop. The

output voltage settling behavior is related to the stabil-

ity of the closed-loop system. The external compensa-

tion, forced continuous operation circuit in the Typical

Applications section uses faster compensation to improve

load step response.

A second, more severe transient is caused by switching

in loads with large (>1ÂµF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT, causing a rapid drop in VOUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. More output

capacitance may be required depending on the duty cycle

and load step requirements.

If the ITH pin is tied to SVIN, the internal compensation

is selected.

VIN = 3.3V

VOUT = 1.8V

ILOAD = 600mA TO 2A

COMPENSATION AND OUTPUT

CAPACITOR VALUES OF FIGURE 3

3618 F05

Figure 5. Load Step Transient in FCM with

External Compensation

3618fc

For more information www.linear.com/LTC3618

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