LTC3618_15 Datasheet, PDF (13/24 Pages) Linear Technology – Dual 4MHz, 3A Synchronous Buck Converter for DDR Termination

Applications Information
V_{IN LTC3618}
SV_IN
RT
f_SW
2.25MHz
V_IN
0.4V
R_T
LTC3618
SV_IN
RT
SGND
f_SW ∝1/R_OSC
LTC3618
V_{IN LTC3618}
SV_IN
f_SW
MODE/SYNC ^1/TP
1.2V
0.3V
T_P
SGND
3618 F04
Figure 4. Setting the Switching Frequency
Frequency Synchronization
The LTC3618’s internal oscillator can be synchronized to
an external frequency by applying a square wave clock
signal to the MODE/SYNC pin. During synchronization,
the top MOSFET turn-on of V_DDQ is locked to the rising
edge of the external frequency source. The synchronization
frequency range is 400kHz to 4MHz. The internal slope
compensation is automatically adapted to the external
clock frequency.
In the signal path from the MODE/SYNC clock input to the
SW output, the LTC3618 is processing the external clock
frequency through an internal PLL.
After detecting an external clock on the first rising edge of
MODE/SYNC the PLL starts up with the internal default of
2.25MHz. The internal PLL then requires a certain number
of periods to settle until the frequency at SW matches the
frequency and phase of MODE/SYNC.
When the external clock signal is removed, the LTC3618
needs approximately 5µs to detect the absence of the
external clock. During this time, the PLL will continue to
provide clock cycles before it is switched back to the de-
fault frequency or selected frequency (set via the external
R_T resistor).
In general, any abrupt clock frequency change of the
regulator will have an effect on the SW pin timing and
may cause equally sudden output voltage changes. This
must be taken into account in particular if the external
clock frequency is significantly different from the internal
default of 2.25MHz.
Phase Selection
V_TT will operate in-phase, 180° out-of-phase (anti-phase)
or shifted by 90° from V_DDQ depending on the state of the
PHASE pin—low, midrail or high, respectively. Antiphase
generally reduces input voltage and current ripple. Cross-
talk between switch nodes SW1, SW2 and components
or sensitive lines connected to FBx, ITHx, RT can cause
unstable switching waveforms and unexpectedly large
input and output voltage ripple.
The situation improves if rising and falling edges of the
switch nodes are timed carefully not to coincide. Depending
on the duty cycle of the two channels, choose the phase
difference between the channels to keep edges as far away
from each other as possible.
For a duty cycle of less than 40% for one channel and more
than 60% for the other channel, choose a phase shift of 0
or 180° (PHASE = SGND or SV_IN). If both channels have
a duty cycle of around 50%, select a phase difference of
90° (PHASE = one-half SV_IN).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the inductor ripple
current. The ripple current ∆I_L increases with higher V_IN
and decreases with higher inductance.
I_L =
V_OUT
f_SW • L
•
1– ^VOUT
V_IN(MAX)
Having a lower ripple current reduces the core losses
in the inductor, the ESR losses in the output capacitors
and the output voltage ripple. A reasonable starting point
for selecting the ripple current is ∆I_L = 0.3(I_OUT(MAX)).
For more information www.linear.com/LTC3618
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