LTC3862 Datasheet, PDF (35/40 Pages) Linear Technology – Multi-Phase Current Mode Step-Up DC/DC Controller

LTC3862
APPLICATIONS INFORMATION
10. The output resistor divider should be located as
close as possible to the IC, with the bottom resistor
connected between FB and SGND. The PCB trace
connecting the top resistor to the upper terminal of
the output capacitor should avoid any high frequency
switching nodes.
11. Since the inductor acts like a current source in a
peak current mode control topology, its placement
on the board is less critical than the high di/dt com-
ponents.
12. The SENSE⁺ and SENSE^– PCB traces should be routed
parallel to one another with minimum spacing in be-
tween all the way to the sense resistor. These traces
should avoid any high frequency switching nodes in
the layout. These PCB traces should also be Kelvin-
connected to the interior of the sense resistor pads,
in order to avoid sensing errors due to parasitic PCB
resistance IR drops.
13. If an external RC filter is used between the sense
resistor and the SENSE⁺ and SENSE^– pins, these filter
components should be placed as close as possible to
the SENSE⁺ and SENSE^– pins of the IC. Ensure that
the SENSE^– line is connected to the ground only at the
point where the current sense resistor is grounded.
14. Keep the MOSFET drain nodes (SW1, SW2) away
from sensitive small-signal nodes, especially from
the opposite channel’s current-sensing signals. The
SW nodes can have slew rates in excess of 1V/ns
relative to ground and should therefore be kept on
the “output side” of the LTC3862.
15. Check the stress on the power MOSFETs by indepen-
dently measuring the drain-to-source voltages directly
across the devices terminals. Beware of inductive
ringing that could exceed the maximum voltage rating
of the MOSFET. If this ringing cannot be avoided and
exceeds the maximum rating of the device, choose
a higher voltage rated MOSFET or consider using a
snubber.
16. When synchronizing the LTC3862 to an external clock,
use a low impedance source such as a logic gate to
drive the SYNC pin and keep the lead as short as
possible.
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