LTC3862 Datasheet, PDF (20/40 Pages) Linear Technology – Multi-Phase Current Mode Step-Up DC/DC Controller

LTC3862
OPERATION
the slope compensation is too low the converter can
suffer from excessive jitter or, worst case, sub-harmonic
oscillation. When excess slope compensation is applied to
the internal current sense signal, the phase margin of the
control loop suffers. Figure 11 illustrates inductor current
waveforms for a properly compensated loop.
The LTC3862 contains a patented circuit whereby most
of the applied slope compensation is recovered, in order
to provide a SENSE⁺ to SENSE^– threshold which is not
a strong function of the duty cycle. This sense threshold
is, however, a function of the programmed slope gain, as
shown in Figure 12. The data sheet typical specification of
75mV for SENSE⁺ minus SENSE^– is measured at a normal-
ized slope gain of 1.00 at low duty cycle. For applications
where the normalized slope gain is not 1.00, use Figure 12
to determine the correct value of the sense resistor.
I_LOAD
2A/DIV
200mA-3A
I_L1
2A/DIV
I_L2
2A/DIV
V_OUT
2V/DIV
V_IN = 24V
V_OUT = 48V
10μs/DIV
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Figure 11. Inductor Current Waveforms for a
Properly Compensated Control Loop
80
75
SLOPE = 0.625
70
SLOPE = 1
SLOPE = 1.66
65
60
55
50
0 10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
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Figure 12. Effect of Slope Gain on the Peak SENSE Threshold
20
Programmable Blanking and the Minimum On-Time
The BLANK pin on the LTC3862 allows the user to program
the amount of leading edge blanking at the SENSE pins.
Connecting the BLANK pin to SGND results in a minimum
on-time of 180ns, floating the pin increases this time to
260ns, and connecting the BLANK pin to the 3V8 supply
results in a minimum on-time of 340ns. The majority
of the minimum on-time consists of this leading edge
blanking, due to the inherently low propagation delay
of the current comparator (25ns typ) and logic circuitry
(10ns to 15ns).
The purpose of leading edge blanking is to filter out noise on
the SENSE pins at the leading edge of the power MOSFET
turn-on. During the turn-on of the power MOSFET the gate
drive current, the discharge of any parasitic capacitance
on the SW node, the recovery of the boost diode charge,
and parasitic series inductance in the high di/dt path all
contribute to overshoot and high frequency noise that
could cause false-tripping of the current comparator. Due
to the wide range of applications the LTC3862 is well-suited
to, fixing one value of the internal leading edge blanking
time would have required the longest delay time to have
been used. Providing a means to program the blank time
allows users to optimize the SENSE pin filtering for each
application. Figure 13 illustrates the effect of the program-
mable leading edge blank time on the minimum on-time
of a boost converter.
Programmable Maximum Duty Cycle
In order to maintain constant frequency and a low output
ripple voltage, a single-ended boost (or flyback or SEPIC)
converter is required to turn off the switch every cycle
for some minimum amount of time. This off-time allows
the transfer of energy from the inductor to the output
capacitor and load, and prevents excessive ripple current
and voltage. For inductor-based topologies like boost and
SEPIC converters, having a maximum duty cycle as close
as possible to 100% may be desirable, especially in low
V_IN to high V_OUT applications. However, for transformer-
based solutions, having a maximum duty cycle near 100%
is undesirable, due to the need for V • sec reset during the
primary switch off-time.
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