LTC3862 Datasheet, PDF (22/40 Pages) Linear Technology – Multi-Phase Current Mode Step-Up DC/DC Controller

LTC3862
OPERATION
The SENSE⁺ and SENSE^– Pins
The SENSE⁺ and SENSE^– pins are high impedance inputs
to the CMOS current comparators for each channel.
Nominally, there is no DC current into or out of these
pins. There are ESD protection diodes connected from
these pins to SGND, although even at hot temperature the
leakage current into the SENSE⁺ and SENSE^– pins should
be less than 1μA.
Since the LTC3862 contains leading edge blanking, an
external RC filter is not required for proper operation.
However, if an external filter is used, the filter components
should be placed close to the SENSE⁺ and SENSE^– pins on
the IC, as shown in Figure 15. The positive and negative
sense node traces should then run parallel to each other
to a Kelvin connection underneath the sense resistor, as
shown in Figure 16. Sensing current elsewhere on the
board can add parasitic inductance and capacitance to
the current sense element, degrading the information
at the sense pins and making the programmed current
limit unpredictable. Avoid the temptation to connect the
SENSE^– line to the ground plane using a PCB via; this
could result in unpredictable behavior.
The sense resistor should be connected to the source
of the power MOSFET and the ground node using short,
wide PCB traces, as shown in Figure 16. Ideally, the bot-
tom terminal of the sense resistors will be immediately
adjacent to the negative terminal of the output capacitor,
since this path is a part of the high di/dt loop formed by
the switch, boost diode, output capacitor and sense resis-
tor. Placement of the inductors is less critical, since the
current in the inductors is a triangle waveform.
Checking the Load Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V_OUT shifts by an
amount equal to ΔI_LOAD (ESR), where ESR is the effective
series resistance of C_OUT. ΔI_LOAD also begins to charge or
discharge C_OUT, generating the feedback error signal that
forces the regulator to adapt to the current change and
return V_OUT to its steady-state value. During this recovery
time V_OUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem.
The availability of the ITH pin not only allows optimization
of control loop behavior but also provides a DC-coupled
and AC-filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin.
V_IN
INTV_CC
LTC3862
GATE
SENSE⁺
SENSE^–
PGND
V_IN
V_OUT
R_SENSE
3862 F15
FILTER COMPONENTS
PLACED NEAR
SENSE PINS
Figure 15. Proper Current Sense Filter Component Placement
MOSFET SOURCE
R_SENSE
TO SENSE
FILTER NEXT
TO CONTROLLER
3862 F16
GND
Figure 16. Connecting the SENSE⁺ and SENSE^– Traces to the
Sense Resistor Using a Kelvin Connection
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