LTC3862 Datasheet, PDF (13/40 Pages) Linear Technology – Multi-Phase Current Mode Step-Up DC/DC Controller

LTC3862
OPERATION
In multi-phase applications, all of the FB pins are connected
together and all of the error amplifier output pins (ITH) are
connected together. The INTV_CC pins, however, should not
be connected together. The INTV_CC regulator is capable of
sourcing current but is not capable of sinking current. As
a result, when two or more INTV_CC regulator outputs are
connected together, the highest voltage regulator supplies
all of the gate drive and control circuit current, and the
other regulators are off. This would place a thermal burden
on the highest output voltage LDO and could cause the
maximum die temperature to be exceeded. In multi-phase
LTC3862 applications, each INTV_CC regulator output should
be independently bypassed to its respective PGND pin as
close as possible to each IC.
The Low Voltage Analog and Digital Supply LDO (3V8)
The second LDO within the LTC3862 is powered off of
INTV_CC and serves as the supply to the low voltage analog
and digital control circuitry, as shown in Figure 1. The
output voltage of this LDO (which also has a PMOS out-
put device) is 3.8V. Most of the analog and digital control
circuitry is powered from the internal 3V8 LDO. The 3V8
pin should be bypassed to SGND with a 1nF ceramic ca-
pacitor (X5R or better), placed as close as possible to the
IC pins. This LDO is not intended to be used as a supply
for external circuitry.
Thermal Considerations and Package Options
The LTC3862 is offered in two package options. The 5mm
× 5mm QFN package (UH24) has a thermal resistance
R_TH(JA) of 34°C/W, the 24-pin TSSOP (FE24) package has a
thermal resistance of 38°C/W, and the 24-pin SSOP (GN24)
package has a thermal resistance of 85°C/W. The QFN and
TSSOP package options have a lead pitch of 0.65mm, and
the GN24 option has a lead pitch of 0.025in.
The INTV_CC regulator can supply up to 50mA of total
current. As a result, care must be taken to ensure that
the maximum junction temperature of the IC is never
exceeded. The junction temperature can be estimated
using the following equations:
I_Q(TOT) = I_Q + Q_G(TOT) • f
P_DISS = V_IN • (I_Q + Q_G(TOT) • f)
T_J = T_A + P_DISS • R_TH(JA)
The total quiescent current (I_Q(TOT)) consists of the static
supply current (I_Q) and the current required to charge
the gate capacitance of the power MOSFETs. The value
of Q_G(TOT) should come from the plot of V_GS vs Q_G in the
Typical Performance Characteristics section of the MOSFET
data sheet. The value listed in the electrical specifications
may be measured at a higher V_GS, such as 10V, whereas the
value of interest is at the 5V INTV_CC gate drive voltage.
As an example of the required thermal analysis, consider
a 2-phase boost converter with a 9V to 24V input voltage
range and an output voltage of 48V at 2A. The switching
frequency is 150kHz and the maximum ambient tempera-
ture is 70°C. The power MOSFET used for this application
is the Vishay Si7478DP, which has a typical R_DS(ON) of
8.8mΩ at V_GS = 4.5V and 7.5mΩ at V_GS = 10V. From the
plot of V_GS vs Q_G, the total gate charge at V_GS = 5V is
50nC (the temperature coefficient of the gate charge is
low). One power MOSFET is used for each phase. For the
QFN package option:
I_Q(TOT) = 3mA + 2 • 50nC • 150kHz = 18mA
P_DISS = 24V • 18mA = 432mW
T_J = 70°C + 432mW • 34°C/W = 84.7°C
In this example, the junction temperature rise is only 14.7°C.
These equations demonstrate how the gate charge current
typically dominates the quiescent current of the IC, and
how the choice of package option and board heat sinking
can have a significant effect on the thermal performance
of the solution.
3862fb
13