LTC3553-2_15 Datasheet, PDF (28/36 Pages) Linear Technology – Micropower USB Power Manager with Li-Ion Charger, Always-On LDO and Buck Regulator

LTC3553-2
OPERATION
present, the same operation would take place with a valid
external supply (V_BUS) with or without a battery present.
The PGOOD remains asserted through this state transition
as the LDO stays on.
Holding ON low through the one second power-down
period will not cause a power-up event at end of the one
second period. The ON pin must be brought high following
the power-down event and then go low again to establish
a valid power-up event.
UVLO Minimum Off-Time Timing (Low Battery)
Figure 10 assumes the battery is either missing or at a
voltage below the V_OUT UVLO threshold, and the applica-
tion is running via external power (V_BUS). A glitch on the
external supply causes V_OUT to drop below the V_OUT UVLO
threshold temporarily. This V_OUT UVLO condition causes
the pushbutton circuitry to transition from the PON state
to the PDN2 state. Upon entering the PDN2 state the buck
regulator powers down. The V_OUT UVLO condition also
disables the LDO causing the PGOOD to go low. Once the
LDO powers back up and is in regulation for 1.8ms, the
PGOOD will go high impedance.
In the typical case where the BUCK_ON pin is driven by
logic powered by the buck regulator, the BUCK_ON pin
would also go low, as depicted in Figure 10. If the exter-
nal supply recovers after entering the PDN2 state such
that V_OUT is no longer in UVLO, then the LTC3553-2 will
transition back into the PUP2 state once the PDN2 one
second delay is complete. Following the state diagram,
the transition from PDN2 to PUP2 in this case actually
occurs via a brief visit to the POFF state. During the brief
1
BAT
0
1
V_BUS
0
1
ON (PB)
0
1
PBSTAT
0
1
BUCK_ON
0
1
BUCK
0
1
LDO
0
1
PGOOD
0
STATE
PON
5s
1s, BUCK POWERS UP
LDO POWERS UP
1.8ms
PDN2
PUP2
PON
35532 F10
Figure 10. UVLO Minimum Off-Time Timing
35532f
28