LTC3553-2_15 Datasheet, PDF (23/36 Pages) Linear Technology – Micropower USB Power Manager with Li-Ion Charger, Always-On LDO and Buck Regulator

LTC3553-2
OPERATION
The switching regulator input supply should be bypassed
with a 2.2μF capacitor. Consult with capacitor manu-
facturers for detailed information on their selection and
specifications of ceramic capacitors. Many manufacturers
now offer very thin (<1mm tall) ceramic capacitors ideal
for use in height-restricted designs. Table 2 shows a list
of several ceramic capacitor manufacturers.
ALWAYS-ON LOW DROPOUT LINEAR REGULATOR
(LDO)
The LDO regulator supports a load of up to 150mA. The
LDO takes power from the V_INLDO pin and drives the LDO
output pin with the goal of bringing the LDO_FB feedback
pin voltage to 0.8V. Usually, a resistor divider is connected
between the LDO’s output pin, feedback pin and ground,
in order to close the control loop and program the output
voltage. For stability, the LDO output must be bypassed
to ground with at least a 1μF ceramic capacitor.
The LDO is enabled whenever the LTC3553-2 is not in
hard reset state. In hard reset state, an internal pull-down
resistor is switched in to help bring the output to ground.
When the LDO is enabled, a soft-start circuit ramps its
regulation point from zero to final value over a period of
roughly 0.2ms, reducing the required V_INLDO inrush current.
The LDO has two input voltage requirements. The LDO’s
quiescent bias current is supplied through an internal
connection to the USB PowerPath V_OUT pin. The LDO’s
power input is taken from the V_INLDO pin. For proper LDO
operation, the V_INLDO pin must be connected to a voltage
no greater than V_OUT. Connecting V_INLDO to a voltage
exceeding V_OUT may result in loss of regulation.
Output Voltage Programming
Figure 4 shows the LDO regulator application circuit.
Program the LDO output voltage, V_LDO, by choosing R1
and R2 such that:
V_LDO
=
0.8V
•
⎛
⎝⎜
R1
R2
+
⎞
1_⎠⎟
LDO
ENABLE
0
1
V_INLDO
MP
LDO
R1
LDO_FB
0.8V
R2
GND
LDO
OUTPUT
C_OUT
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Figure 4. LDO Application Circuit
PGOOD Operation
The PGOOD pin is an open-drain output which indicates that
all enabled regulators have reached their final regulation
voltage. It goes high impedance 1.8ms after all enabled
regulators reach 92% of their regulation value. The delay
allows time for an external processor to reset itself. PGOOD
may be used as a power-on reset to a microprocessor
powered by the buck regulator. Since PGOOD is an open-
drain output, a pull-up resistor to an appropriate power
source is needed. A suggested approach is to connect
the pull-up resistor to the LDO output or V_OUT pin so that
power is not dissipated while in hard reset state.
V_OUT UNDERVOLTAGE LOCKOUT (V_OUT UVLO)
An undervoltage lockout circuit on the USB PowerPath
V_OUT pin shuts down and prevents both the buck and
the LDO from enabling when the V_OUT pin voltage drops
below about 2.6V.
Buck Regulator UVLO Considerations
It is recommended that the buck regulator input supply
(BVIN pin) be connected directly to the USB PowerPath
output (V_OUT pin). With this connection, the V_OUT UVLO
prevents the buck regulator from operating at low input
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