LTC3788 Datasheet, PDF (26/32 Pages) Linear Technology – 2-Phase, Dual Output Synchronous Boost Controller

LTC3788
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 7. Figure 8 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Put the bottom N-channel MOSFETs MBOT1 and MBOT2
and the top N-channel MOSFETs MTOP1 and MTOP2
in one compact area with C_OUT.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C_INTVCC must return to the combined C_OUT (–) terminals.
The path formed by the bottom N-channel MOSFET and
the C_IN capacitor should have short leads and PC trace
lengths. The output capacitor (–) terminals should be
connected as close as possible to the (–) terminals of
the input capacitor by placing the capacitors next to
each other.
3. Do the LTC3788 VFB pins’ resistive dividers connect to
the (+) terminals of C_OUT? The resistive divider must be
connected between the (+) terminal of C_OUT and signal
ground and placed close to the VFB pin. The feedback
resistor connections should not be along the high cur-
rent input feeds from the input capacitor(s).
4. Are the SENSE ^– and SENSE⁺ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE⁺ and SENSE ^– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
5. Is the INTV_CC decoupling capacitor connected close
to the IC, between the INTV_CC and the power ground
pins? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1μF ceramic capacitor placed
immediately next to the INTV_CC and PGND pins can help
improve noise performance substantially.
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6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2) and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and, therefore, should be kept on
the output side of the LTC3788 and occupy a minimal
PC trace area.
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV_CC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output volt-
age. Check for proper performance over the operating
voltage and current range expected in the application. The
frequency of operation should be maintained over the input
voltage range down to dropout and until the output load
drops below the low current operation threshold— typi-
cally 10% of the maximum designed current level in Burst
Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for its individual performance should
both controllers be turned on at the same time. A particu-
larly difficult region of operation is when one controller
channel is nearing its current comparator trip point while
the other channel is turning on its bottom MOSFET. This
occurs around the 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
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