LTC3788 Datasheet, PDF (14/32 Pages) Linear Technology – 2-Phase, Dual Output Synchronous Boost Controller

LTC3788
OPERATION
Frequency Selection and Phase-Locked Loop (FREQ
and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3788’s controllers can
be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTV_CC, or programmed through an external resistor.
Tying FREQ to SGND selects 350kHz while tying FREQ to
INTV_CC selects 535kHz. Placing a resistor between FREQ
and SGND allows the frequency to be programmed between
50kHz and 900kHz, as shown in Figure 6.
A phase-locked loop (PLL) is available on the LTC3788
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3788’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of the first controller’s external bottom MOSFET
to the rising edge of the synchronizing signal. Thus, the
turn-on of the second controller’s external bottom MOSFET
is 180 or 240 degrees out-of-phase to the rising edge of
the external clock source.
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of BG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC3788’s PLL is from
approximately 55kHz to 1MHz, and is guaranteed to
lock to an external clock source whose frequency is be-
tween 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3788 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisychained with the
LTC3788 in PolyPhase^® applications. The clock output
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal as well as the relative phases
between the two internal controllers, as summarized in
Table 1. The phases are calculated relative to the zero
degrees phase being defined as the rising edge of the
bottom gate driver output of controller 1 (BG1).
Table 1.
V_PHASMD
GND
Floating
INTV_CC
CONTROLLER 2
PHASE (°C)
180
180
240
CLKOUT
PHASE (°C)
60
90
120
CLKOUT is disabled when one of the channels is in sleep
mode and another channel is either in shutdown or in
sleep mode.
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