LTC3819 Datasheet, PDF (25/32 Pages) Linear Technology – 2-Phase, High Efficiency, Step-Down Controller for Sun Server CPUs

LTC3819
APPLICATIO S I FOR ATIO
Using Figure 4, the RMS ripple current will be:
I_INRMS = (20A)(0.25) = 5A_RMS
An input capacitor(s) with a 5A_RMS ripple current rating is
required.
The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor
and multiplying by the factor obtained from Figure 3
along with the calculated duty factor. The output ripple in
continuous mode will be highest at the maximum input
voltage since the duty factor is < 50%. The maximum
output current ripple is:
( ) ^∆ICOUT
=
V_OUT
fL
0.5
at 24%D F
( )( ) ^{∆ICOUTMAX =}
1.2V
0.5
300kHz 1.0µH
= 2A_P-P
( ) ^VOUTRIPPLE ^{= 20mΩ 2A}P-P ^{= 40mV}P-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3819. Check the following in your layout:
1) Are the signal and power grounds separate? The signal
ground traces should return to Pin 9 first. Connect Pin 9
to Pin 28 through a wide and straight trace. Then the signal
ground joins the power ground plane beside Pin 28. It is
recommended that the Pin 28 return to the (–) plates of C_IN.
2) Does the LTC3819 V_OS+ pin connect to the point of
load? Does the LTC3819 V_OS– pin connect to the load
return?
3) Are the SENSE ^– and SENSE ⁺ leads routed together with
minimum PC trace spacing? The filter capacitors between
SENSE ⁺ and SENSE^– pin pairs should be as close as
possible to the LTC3819. Ensure accurate current sensing
with Kelvin connections at the current sense resistor. See
Figure 8.
4) Does the (+) plate of C_IN connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the AC current to the MOSFETs. Keep the input
current path formed by the input capacitor, top and bottom
MOSFETs, and the Schottky diode on the same side of the
PC board in a tight loop to minimize conducted and
radiated EMI.
5) Is the INTV_CC 1µF ceramic decoupling capacitor con-
nected closely between INTV_CC and the PGND pin? This
capacitor carries the MOSFET driver peak currents. A
small value is recommended to allow placement immedi-
ately adjacent to the IC.
6) Keep the switching nodes, SW1 (SW2), away from
sensitive small-signal nodes. Ideally the switch nodes
should be placed at the furthest point from the
LTC3819.
7) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.
PADS OF SENSE RESISTOR
TRACE TO INDUCTOR
TRACE TO OUTPUT CAP (+)
SENSE⁺ SENSE ^–
3819 F09
Figure 8. Proper Current Sense Connections
3819f
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