LTC3819 Datasheet, PDF (13/32 Pages) Linear Technology – 2-Phase, High Efficiency, Step-Down Controller for Sun Server CPUs

LTC3819
APPLICATIO S I FOR ATIO
The basic LTC3819 application circuit is shown in
Figure 1 on the first page. External component selection
begins with the selection of the inductors based on ripple
current requirements and continues with the current
sensing resistors using the calculated peak inductor
current and/or maximum current limit. Next, the power
MOSFETs, D1 and D2 are selected. The operating fre-
quency and the inductor are chosen based mainly on the
amount of ripple current. Finally, C_IN is selected for its
ability to handle the input ripple current (that PolyPhase^TM
operation minimizes) and C_OUT is chosen with low enough
ESR to meet the output ripple voltage and load step
specifications (also minimized with PolyPhase). Current
mode architecture provides inherent current sharing be-
tween output stages. The circuit shown in Figure 1 can be
configured for operation up to an input voltage of 28V
(limited by the external MOSFETs). Current mode control
allows the ability to connect the two output stages to two
different input power supply rails. A heavy output load can
take some power from each input supply according to the
selection of the R_SENSE resistors.
R_SENSE Selection For Output Current
R_SENSE1,2 are chosen based on the required peak output
current. The LTC3819 current comparator has a maxi-
mum threshold of 75mV/R_SENSE and an input common
mode range of SGND to 1.1(INTV_CC). The current com-
parator threshold sets the peak inductor current, yielding
a maximum average output current I_MAX equal to the peak
value less half the peak-to-peak ripple current, ∆I_L.
Assuming a common input power source for each output
stage and allowing a margin for variations in the
LTC3819 and external component values yields:
R_SENSE
=
N
50mV
I_MAX
where N = 2 for 2 phase. For more than 2 phase use the
LTC1629-6 plus the LTC3819.
Operating Frequency
The LTC3819 uses a constant frequency, phase-lockable
architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current
plus an additional current which is proportional to the
voltage applied to the PLLFLTR pin. Refer to Phase-
Locked Loop and Frequency Synchronization for addi-
tional information.
A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure 2. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 310kHz.
2.5
2.0
1.5
1.0
0.5
0
120
170
220
270
320
OPERATING FREQUENCY (kHz)
3819 F02
Figure 2. Operating Frequency vs V_PLLFLTR
Inductor Value Calculation and Output Ripple Current
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
MOSFET gate charge and transition losses increase
directly with frequency. In addition to this basic tradeoff,
the effect of inductor value on ripple current and low
current operation must also be considered. The PolyPhase
approach reduces both input and output ripple currents
while optimizing individual output stages to run at a lower
fundamental frequency, enhancing efficiency.
The inductor value has a direct effect on ripple current.
The inductor ripple current ∆I_L per individual section, N,
decreases with higher inductance or frequency and
increases with higher V_IN or V_OUT:
PolyPhase is a registered trademark of Linear Technology Corporation.
3819f
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