LTC3819 Datasheet, PDF (21/32 Pages) Linear Technology – 2-Phase, High Efficiency, Step-Down Controller for Sun Server CPUs

LTC3819
APPLICATIO S I FOR ATIO
The loop filter components (C_LP, R_LP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C_LP and R_LP determine how fast the loop
acquires lock. Typically R_LP =10k and C_LP is 0.01µF to
0.1µF.
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest time duration
that the LTC3819 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that:
( ) ^{( ) tON MIN}
< ^VOUT
V_IN f
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3819 will begin to skip
cycles resulting in variable frequency operation. The out-
put voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the LTC3819 is generally less
than 200ns. However, as the peak sense voltage de-
creases, the minimum on-time gradually increases. This is
of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre-
spondingly larger ripple current and voltage ripple.
If an application can operate close to the minimum
on-time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement. As a general
rule, keep the inductor ripple current of each phase equal
to or greater than 15% of I_OUT(MAX) at V_IN(MAX).
FCB Pin Operation
The following table summarizes the possible states avail-
able on the FCB pin:
Table 2
FCB Pin
0V to 0.55V
0.65V < V_FCB < 4.3V (typ)
> 4.8V
Condition
Forced Continuous (Current Reversal
Allowed—Burst Inhibited)
Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
Active Voltage Positioning
Active voltage positioning can be used to minimize peak-
to-peak output voltage excursion under worst-case tran-
sient loading conditions. The open-loop DC gain of the
control loop is reduced depending upon the maximum
load step specifications. Active voltage positioning can
easily be added to the LTC3819 by loading the I_TH pin with
a resistive divider having a Thevenin equivalent voltage
source equal to the midpoint operating voltage of the error
amplifier, or 1.2V (see Figure 7).
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
worst-case peak-to-peak output voltage deviation due to
transient loading can theoretically be reduced to half or
alternatively the amount of output capacitance can
be reduced for a particular application. A complete
explanation is included in Design Solutions 10 or the
LTC1736 data sheet. (See www.linear-tech.com)
INTV_CC
R_T2
R_T1
I_TH
R_C
LTC3819
C_C
3719 F07
Figure 7. Active Voltage Positioning Applied to the LTC3819
3819f
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