LTC3819 Datasheet, PDF (20/32 Pages) Linear Technology – 2-Phase, High Efficiency, Step-Down Controller for Sun Server CPUs

LTC3819
APPLICATIO S I FOR ATIO
condition. When deriving the 5µA current from V_IN as in
the figure, current latchoff is always defeated. The diode
connecting this pull-up resistor to INTV_CC, as in Figure 5,
eliminates any extra supply current during shutdown
while eliminating the INTV_CC loading from preventing
controller start-up.
Why should you defeat current latchoff? During the
prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is com-
plete whether to rely solely on foldback current limiting or
to enable the latchoff feature by removing the pull-up
resistor.
The value of the soft-start capacitor C_SS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C_SS > (C_OUT )(V_OUT)(10^-4)(R_SENSE)
The minimum recommended soft-start capacitor of C_SS =
0.1µF will be sufficient for most applications.
Phase-Locked Loop and Frequency Synchronization
The LTC3819 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the
center frequency f_O. A voltage applied to the PLLFLTR pin
of 1.2V corresponds to a frequency of approximately
220kHz. The nominal operating frequency range of the
LTC3819 is 140kHz to 310kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆f_H, is equal to the capture range, ∆f_C:
∆f_H = ∆f_C = ±0.5 f_O (150kHz-300kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 6.
EXTERNAL
OSC
2.4V
PHASE
DETECTOR
PLLIN
DIGITAL
PHASE/
FREQUENCY
50k
DETECTOR
R_LP
10k
C_LP
PLLFLTR
OSC
3719 F06
Figure 6. Phase-Locked Loop Block Diagram
If the external frequency (f_PLLIN) is greater than the oscil-
lator frequency f_0SC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f_0SC, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal fre-
quencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time correspond-
ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor C_LP holds the voltage. The
LTC3819 PLLIN pin must be driven from a low impedance
source such as a logic gate located close to the pin.
3819f
20