LTC3836_15 Datasheet, PDF (23/30 Pages) Linear Technology – Dual 2-Phase, No RSENSETM Low VIN Synchronous Controller

LTC3836
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3836. These items are illustrated in the layout diagram of
Figure 13. Figure 14 depicts the current waveforms present
in the various branches of the 2-phase dual regulator.
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small
as possible and isolated as much as possible from the
power loop of the other channel. Ideally, the main and
synchronous FETs should be connected close to one
another with an input capacitor placed right at the FETs.
It is better to have two separate, smaller valued input
capacitors (e.g., two 10μF —one for each channel) than
it is to have a single larger valued capacitor (e.g., 22μF)
that the channels share with a common connection.
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor divid-
ers, I_TH compensation networks and the SGND pin.
The power grounds consist of the (–) terminal of the
input and output capacitors and the source of the
synchronous N-channel MOSFET. Each channel should
have its own power ground for its power loop (as de-
scribed above in item 1). The power grounds for the
two channels should connect together at a common
point. It is most important to keep the ground paths
with high switching currents away from each other.
The PGND pins on the LTC3836 should be shorted
together and connected to the common power ground
connection (away from the switching currents).
3) Put the feedback resistors close to the V_FB pins. The
trace connecting the top feedback resistor (R_B) to
the output capacitor should be a Kelvin trace. The I_TH
compensation components should also be very close
to the LTC3836.
4) The current sense traces (SENSE⁺ and SW) should be
Kelvin connections right at the main N-channel MOSFET
drains and sources.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-
signal components, especially the opposite channel’s
feedback resistors, I_TH compensation components, and
the current sense pins (SENSE⁺ and SW).
6) Connect the boost capacitors to the switch nodes, not to
the small signal nodes SWn. Connect the boost diodes
to the positive terminal of the input capacitor.
LTC3836EGN
1 _SW1
2 _N/C
SENSE1^{+ 28}
27
BOOST1
3 _IPRG1
4 _VFB1
5 _ITH1
6 _IPRG2
7 _PLLLPF
26
PGND
BG1 ²⁵
SYNC/FCB ²⁴
TG1 ²³
22
PGND
8 _SGND
21
TG2
9 _VIN
10 _TRACK/SS2
RUN/SS ²⁰
BG2 ¹⁹
11 _VFB2
12 _ITH2
13 _PGOOD
N/C ¹⁸
PGND ¹⁷
BOOST2 ¹⁶
SENSE2^{+ 15}
SW2 ¹⁴
BOLD LINES INDICATE HIGH CURRENT PATHS
C_OUT1
C_B1
V_OUT1
L1
D_B1
D_B2
C_B2
M1
C_VIN1
C_VIN
C_VIN2
M3
M2
V_IN
M4
C_OUT2
L2
V_OUT2
3836 F13
Figure 13. LTC3836 Layout Diagram
3836fb
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