LTC3836_15 Datasheet, PDF (20/30 Pages) Linear Technology – Dual 2-Phase, No RSENSETM Low VIN Synchronous Controller

LTC3836
APPLICATIONS INFORMATION
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor C_LP holds the voltage.
The loop filter components, C_LP and R_LP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components C_LP and R_LP determine how fast the loop
acquires lock. Typically R_LP = 10k and C_LP is 2200pF to
0.01μF.
Typically, the external clock (on SYNC/FCB pin) input high
level is 1.6V, while the input low level is 1.2V.
Table 1 summarizes the different states in which the
PLLLPF pin can be used.
Table 1.
PLLLPF PIN
0V
Floating
V_IN
RC Loop Filter
SYNC/FCB PIN
DC Voltage
DC Voltage
DC Voltage
Clock Signal
FREQUENCY
300kHz
550kHz
750kHz
Phase-Locked to External Clock
Topside MOSFET Drive Supply (C_B, D_B)
In the Functional Diagram, external bootstrap capaci-
tor C_B is charged from a boost power source (usually
V_IN) through diode D_B when the SW node is low. When
a MOSFET is to be turned on, the C_B voltage is applied
across the gate-source of the desired device. When the
topside MOSFET is on, the BOOST pin voltage is above
the input supply. V_BOOST = 2V_IN. C_B must be 100 times the
total input capacitance of the topside MOSFET. The reverse
breakdown of D_B must be greater than V_IN(MAX). Figure 6
shows how a 5V gate drive can be achieved if a secondary
5V supply is available. Note that in applications where the
supply voltage to C_B exceeds V_IN, the BOOST pin will draw
approximately 500μA in shutdown mode.
Table 2 summarizes the different states in which the
SYNC/FCB pin can be used
Table 2.
SYNC/FCB PIN
0V to 0.5V
0.7V to V_IN
External Clock Signal
CONDITION
Forced Continuous Mode
Current Reversal Allowed
Pulse-Skipping Operation Enabled
No Current Reversal Allowed
Enable Phase-Locked Loop
(Synchronize to External CLK)
Pulse-Skipping at Light Loads
No Current Reversal Allowed
Fault Condition: Short-Circuit and Current Limit
To prevent excessive heating of the bottom MOSFET,
foldback current limiting can be added to reduce the cur-
rent in proportion to the severity of the fault.
Foldback current limiting is implemented by adding
diodes D_FB1 and D_FB2 between the output and the I_TH
pin as shown in Figure 11. In a hard short (V_OUT = 0V),
the current will be reduced to approximately 50% of the
maximum output current.
1/2 LTC3836
I_TH
V_FB
R2 ₊
R1
V_OUT
D_FB1
D_FB2
3836 F11
Figure 11. Foldback Current Limiting
3836fb
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