LTC3836_15 Datasheet, PDF (16/30 Pages) Linear Technology – Dual 2-Phase, No RSENSETM Low VIN Synchronous Controller

LTC3836
APPLICATIONS INFORMATION
Inductor Core Selection
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Schottky Diode Selection (Optional)
The Schottky diodes D1 and D2 in Figure 16 conduct
current during the dead time between the conduction of
the power MOSFETs . This prevents the body diode of
the bottom MOSFET from turning on and storing charge
during the dead time, which could cost as much as 1% in
efficiency. A 1A Schottky diode is generally a good size for
most LTC3836 applications, since it conducts a relatively
small average current. Larger diodes result in additional
transition losses due to their larger junction capacitance.
This diode may be omitted if the efficiency loss can be
tolerated.
C_IN and C_OUT Selection
The selection of C_IN is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can be
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
the highest (V_OUT)(I_OUT) product needs to be used in the
formula below to determine the maximum RMS capacitor
current requirement. Increasing the output current drawn
from the other controller will actually decrease the input
RMS ripple current from its maximum value. The out-of-
phase technique typically reduces the input capacitor’s RMS
ripple current by a factor of 30% to 70% when compared
to a single phase power supply solution.
In continuous mode, the source current of the main N-chan-
nel MOSFET is a square wave of duty cycle (V_OUT)/(V_IN). To
prevent large voltage transients, a low ESR capacitor sized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
( )( ) ^C_IN
Re
quired
I_RMS


I_MAX
V_IN

V_OUT
V_IN – V_OUT ^1/2
This formula has a maximum at V_IN = 2V_OUT, where I_RMS
= I_OUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3836, ceramic capacitors
can also be used for C_IN. Always consult the manufacturer
if there is any question.
The benefit of the LTC3836 2-phase operation can be cal-
culated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the same
time. The total RMS power lost is lower when both control-
lers are operating due to the reduced overlap of current
pulses required through the input capacitor’s ESR. This is
why the input capacitor’s requirement calculated above for
the worst-case controller is adequate for the dual controller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system. The overall benefit of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the efficiency testing.
The drains of the main MOSFETs should be placed within
1cm of each other and share a common C_IN(s). Separating
the drains and C_IN may produce undesirable voltage and
current resonances at V_IN.
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