LTC3836_15 Datasheet, PDF (22/30 Pages) Linear Technology – Dual 2-Phase, No RSENSETM Low VIN Synchronous Controller

LTC3836
APPLICATIONS INFORMATION
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of
the losses in LTC3836 circuits: 1) LTC3836 DC bias cur-
rent, 2) MOSFET gate charge current, 3) I²R losses, and
4) transition losses.
1) The V_IN (pin) current is the DC supply current, given
in the electrical characteristics, excluding MOSFET
driver currents. V_IN current results in a small loss that
increases with V_IN.
2) MOSFET gate charge current results from switching the
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from SENSE⁺ to ground.
The resulting dQ/dt is a current out of SENSE⁺, which
is typically much larger than the DC supply current. In
continuous mode, I_GATECHG = f • Q_P.
3) I²R losses are calculated from the DC resistances of the
MOSFETs and inductor. In continuous mode, the average
output current flows through L but is “chopped” between
the top MOSFET and the bottom MOSFET. The MOSFET
R_DS(ON)s multiplied by duty cycle can be summed with
the resistance of L to obtain I²R losses.
4) Transition losses apply to the top MOSFET and increase
with higher operating frequencies and input voltages.
Transition losses can be estimated from:
Transition Loss = 2 (V_IN)²I_O(MAX)C_RSS(f)
Other losses, including C_IN and C_OUT ESR dissipative losses
and inductor core losses, generally account for less than
2% total additional loss.
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Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to (∆I_LOAD)(ESR), where ESR is the effective series
resistance of C_OUT. ∆I_LOAD also begins to charge or dis-
charge C_OUT, which generates a feedback error signal. The
regulator loop then returns V_OUT to its steady-state value.
During this recovery time, V_OUT can be monitored for
overshoot or ringing. OPTI-LOOP^® compensation allows
the transient response to be optimized over a wide range
of output capacitance and ESR values.
The I_TH series R_C-C_C filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The I_TH external
components shown in the Typical Application on the front
page of this data sheet will provide an adequate starting point
for most applications. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be decided upon
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1μs to
10μs will produce output voltage and I_TH pin waveforms that
will give a sense of the overall loop stability. The gain of the
loop will be increased by increasing R_C, and the bandwidth
of the loop will be increased by decreasing C_C. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance. For a detailed explanation of optimiz-
ing the compensation components, including a review of
control loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C_LOAD).
Thus a 10μF capacitor would require a 250μs rise time,
limiting the charging current to about 200mA.
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