LTC3836_15 Datasheet, PDF (19/30 Pages) Linear Technology – Dual 2-Phase, No RSENSETM Low VIN Synchronous Controller

LTC3836
APPLICATIONS INFORMATION
For coincident tracking,
t_SS2
=
t_SS1
•
V_OUT2F
V_OUT1F
where V_OUT1F and V_OUT2F are the final, regulated values
of V_OUT1 and V_OUT2. V_OUT1 should always be greater than
V_OUT2 when using the TRACK/SS2 pin for tracking. If no
tracking function is desired, then the TRACK/SS2 pin may
be tied to a capacitor to ground, which sets the ramp time
to final regulated output voltage.
Phase-Locked Loop and Frequency Synchronization
The LTC3836 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the main N-channel
MOSFET of controller 1 to be locked to the rising edge
of an external clock signal applied to the SYNC/FCB pin.
The turn-on of controller 2’s main N-channel MOSFET is
thus 180 degrees out-of-phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the external filter
network connected to the PLLLPF pin. The relationship
between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
FCB, is shown in Figure 8 and specified in the Electrical
Characteristics table. Note that the LTC3836 can only be
synchronized to an external clock whose frequency is within
range of the LTC3836’s internal VCO, which is nominally
200kHz to 1MHz. This is guaranteed, over temperature
and variations, to be between 300kHz and 750kHz. A
simplified block diagram is shown in Figure 9.
If the external clock frequency is greater than the internal
oscillator’s frequency, f_OSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f_OSC, current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
1400
1200
1000
800
600
400
200
0
0
0.5
1
1.5
2 2.4
PLLLPF PIN VOLTAGE (V)
3836 F08
Figure 8. Relationship Between Oscillator Frequency
and Voltage at the PLLLPF Pin When Synchronizing to
an External Clock
EXTERNAL
OSCILLATOR
SYNC/
FCB
DIGITAL
PHASE/
FREQUENCY
DETECTOR
2.4V
R_LP
C_LP
PLLLPF
OSCILLATOR
3836 F09
Figure 9. Phase-Locked Loop Block Diagram
3836fb
19