LTC3854_15 Datasheet, PDF (21/28 Pages) Linear Technology – Small Footprint, Wide VIN Range Synchronous Step-Down DC/DC Controller

LTC3854
APPLICATIONS INFORMATION
However, the amount of capacitance needed is determined
not only by the allowed ripple in steady state but by the
maximum energy stored in the inductor. The capacitance
must be sufficient in value to absorb the change in induc-
tor current when a high current to low current transient
occurs. The minimum capacitance to assure the inductor’s
energy is adequately absorbed during a 5A load step for
a maximum overshoot of 2% is:
C_OUT
≥
2
•
L • ∆I_L2
∆V_OUT • V_OUT
C_OUT
≥
0.56µH • (5A)²
0.02 • 1.2V
C_OUT ≥ 583µF
A maximum overshoot or undershoot of 2% for a 5A load
step will require an ESR of:
ESR
<
0.02
•
V_OUT
∆I_LOAD
=
0.02
•
1.2V
5A
≤
5mΩ
Several quality capacitors are available with low enough
ESR.
Multilayer ceramic capacitors tend to have very low ESR
values. It is also a good practice to reduce the ESL by putting
several capacitors in parallel on the output (a parallel bank
of larger and smaller capacitors will improve performance
in both a DC and a transient condition).
To keep ripple very low and design for any possible large
excursions in current 2x 330µF (tantalum or polymer
surface) and 1x 47µF polymer low ESR type were con-
nected in parallel.
Choosing FB Resistors (See Figure 3)
V_OUT
=
0.8 ^{}1+
R_B
R_A


R_B = 0.5R_A
Using 1% 10.0k for R_A gives 1% 4.99k for R_B.
Choosing C_IN Capacitors
C_IN is chosen for a RMS current rating of at least I_OUT(MAX)/2
= 6A. Again, keeping ESR low will improve performance
and reduce power loss (several capacitors in parallel is
once again a good choice). We will use an 180µF 25V
electrolytic with 2x 10µF 25V low ESR ceramic capacitors
connected in parallel.
Choosing MOSFETs
The power dissipation in the main and synchronous FETs
can be easily estimated. Choosing a Renesas RJK0305DPB
for the main FET results in the following parameters:
BV_DSS = 30V
R_DS(ON) = 13mΩ maximum at 25°C, V_GS = 4.5V
Q_GD = 1.5nC at V_DS, test 10V results in C_MILLER = 1.5nC/10V
= 150pF
Q_G = 8nC, typical, at V_GS = 4.5V
V_MILLER = 2.8V
At V_IN = 20V, I_OUT = 15A, estimated T_J = 100°C for the
top FET and given
V_INTVCC = 5.0V
R_DR,PULLUP = 2.6Ω
R_DR,PULLDOWN = 1.5Ω
the total losses in the main FET will be:
( ) ^P_MAIN
=
1.2V
20V
•
(1 5 A )²
•
1+ 0.005 • (100°C – 25°C)
• 13mΩ + (20V )² • ^15A • 150pF
2
•


2.5Ω
5V − 2.8V
+
1.2Ω 
2.8V 
•
f_SW
P_MAIN = 0.55W
3854fb
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