LTC3854_15 Datasheet, PDF (12/28 Pages) Linear Technology – Small Footprint, Wide VIN Range Synchronous Step-Down DC/DC Controller

LTC3854
APPLICATIONS INFORMATION
Inductor Core Selection
Once the value for L is determined, the type of inductor
must be selected. High efficiency converters generally
cannot afford the core loss found in low cost powdered
iron cores, forcing the use of more expensive ferrite or
molypermalloy cores. Actual core loss is independent of
core size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies; allowing design goals to
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode (Optional)
Selection
Two external power MOSFETs must be selected for the
LTC3854 controller: one N-channel MOSFET for the top
(main) switch, and one N-channel MOSFET for the bottom
(synchronous) switch.
The peak-to-peak drive levels are set by the INTV_CC voltage.
This voltage is 5V during start-up. Consequently, logic-
level threshold MOSFETs can be used in most applications.
The only exception is if low input voltage is expected (V_IN
< 5V); then, sub-logic level threshold MOSFETs (V_GS(TH)
< 3V) should be used. Pay close attention to the BV_DSS
specification for the MOSFETs as well; most of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance R_DS(ON), Miller capacitance C_MILLER, input
voltage and maximum output current. Miller capacitance,
C_MILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. C_MILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in V_DS. This result is
12
then multiplied by the ratio of the applied V_DS to the gate
charge curve specified V_DS. When the IC is operating in
continuous mode the duty cycles for the top and bottom
MOSFETs are given by:
Main
Switch
Duty
Cycle =
V_OUT
V_IN
=D
Synchronous
Switch
Duty
Cycle =
V_IN
− V_OUT
V_IN
= 1−D
The MOSFET power dissipations at maximum output
current are given by:
( ) ( ) P_MAIN
=
V_OUT
V_IN
I_MAX
2
1+ δ
R_DS(ON) +
) ) ) ( ( ( ^V_IN
2


I_MAX
2


R_DR
C_MILLER •



V_INTVCC
1
− V_TH(MIN)
+
1
V_TH(MIN)

(f)

( ) ( ) P_SYNC
=
V_IN
− V_OUT
V_IN
I_MAX
2
1+ δ
R_DS(ON)
where δ is the temperature dependency of R_DS(ON) and
R_DR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. V_TH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I²R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V_IN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for V_IN > 20V the transition losses rapidly
increase to the point that the use of a higher R_DS(ON) device
with lower C_MILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
short-circuit when the synchronous switch is on close to
100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R_DS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
3854fb