LTC3765_15 Datasheet, PDF (21/24 Pages) Linear Technology – Active Clamp Forward Controller and Gate Driver

LTC3765
APPLICATIONS INFORMATION
Maximum Duty Cycle
During the delay time between AG rising and PG rising,
power is not transferred from the input supply to the
output supply. In most forward converter systems, the
maximum on-time is artificially limited by the delay, which
then drives a trade-off between the optimal delay time
and the maximum achievable duty cycle. The LTC3765
and LTC3766 implement a unique system in which the
PG and FG rising delays are reduced as the demanded
duty cycle approaches maximum duty cycle. This allows
for greater input voltage range variation over traditional
forward converters.
Be cautious with component selection when designing
with high duty cycles. Recall that the voltage on the drain
of the primary switch is equal to V_IN/(1-D), where D is the
duty cycle. This voltage increases dramatically as the duty
cycle approaches 100%. The LTC3766 limits the maximum
duty cycle to 79% in order to reset the transformer core
without excessive voltage stress on the primary switch.
Pulse Transformer
The pulse transformer that connects the LTC3766 PT⁺/
PT^− outputs to the LTC3765 IN⁺/IN^− inputs functions as the
communication link between the secondary-side controller
and the primary-side gate driver, as shown in Figure 9.
Refer to the LTC3766 data sheet to determine the turns
ratio and volt-second specifications for the pulse trans-
former. Keep in mind that the amplitude of the signals on
the IN⁺ and IN^– pins should be in the range of 4V to 15V
to ensure proper operation.
0.1µF
1µF
IN⁺
LTC3765
••
PT⁺
LTC3766
IN^–
N₃₇₆₅:N₃₇₆₆
PT^–
3765 F09
Figure 9. Pulse Transformer Connection
Furthermore, an additional constraint on the IN⁺/IN^– volt-
age is present when V_CC bias is extracted from the signal.
The internal rectifier drops approximately 1V between the
IN⁺ and IN^– pins and V_CC. Therefore, the signal on the IN⁺
and IN^– pins should be at least 9V to keep the V_CC supply
above its falling UVLO threshold.
The 1µF and 0.1µF capacitors in series with the pulse
transformer of Figure 9 are for blocking and restoring the
DC level of the signal. These values are appropriate for
most LTC3765/LTC3766 applications.
Bypassing and Grounding
The LTC3765 requires proper bypassing on the V_CC supply
due to its high speed switching (nanoseconds) and large
AC currents (Amperes). Careless component placement
and PCB trace routing may cause excessive ringing and
undershoot/overshoot.
To obtain the optimal performance from the LTC3765:
A. Use a low inductance, low impedance ground plane
to reduce any ground drop and stray capacitance.
Remember that the LTC3765 switches greater than
2A peak currents and any significant ground drop will
degrade signal integrity.
B. Mount a bypass capacitor as close as possible between
the V_CC pin and ground plane.
C. Plan the power/ground routing carefully. Know where
the large load switching current is coming from and
going to. Maintain separate ground return paths for
the signal pins and the output power stage.
D. Keep the copper traces between the driver output pins
and the load short and wide.
E. Solder the exposed pad on the back side of the LTC3765
package to the ground plane. The exposed pad is inter-
nally electrically connected to the SGND pin; however,
rated thermal performance will only be achieved if the
exposed pad is soldered to a low impedance ground
plane.
For more information www.linear.com/LTC3765
3765fb
21