LTC3765_15 Datasheet, PDF (20/24 Pages) Linear Technology – Active Clamp Forward Controller and Gate Driver

LTC3765
APPLICATIONS INFORMATION
capacitor is also the voltage seen at the drains of the PG
and AG MOSFETs.
As shown in Figure 8, the V_CL voltage has a minimum when
the converter is operating at 50%. For a given range on
V_IN, therefore, the maximum clamp voltage (V_CL(MAX)) will
occur either at the minimum or maximum V_IN, depending
on which input voltage causes the converter to operate
furthest from 50% duty cycle. The maximum V_CL voltage
can be determined by substituting the maximum and
minimum values of V_IN into this equation and selecting
the larger of the two. In order to leave room for overshoot,
choose a capacitor whose voltage rating is greater than
this maximum V_CL voltage by 50% or more. Typically, a
good quality (X7R) ceramic capacitor is a good choice for
C_CLAMP. Also, be sure to account for the voltage coefficient
of the capacitor. Many ceramic capacitors will lose as much
as 50% of their value at their rated voltage.
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
20 30 40 50 60 70 80
DUTY CYCLE (%)
3765 F08
Figure 8. Active Clamp Capacitor Voltage vs Duty Cycle
In addition to voltage rating, another design constraint
on C_CLAMP occurs because of the resonance between the
magnetizing inductance of the main transformer with the
clamp capacitor. The magnetizing inductance L_MAG and
C_CLAMP form a high-Q resonant system that results in a
sinusoidal ripple on the capacitor voltage. To avoid the
problems associated with this resonance, always use
an RC snubber in parallel with the clamp capacitor as
shown in Figures 7a and 7b. Choose values for the clamp
capacitor and the snubber components according to the
following equations, where f_SW is the frequency set by
the LTC3766 FS pin:
C_CLAMP
=
1
2L_MAG
•


2•
4
π•
f_SW


2
C_SN = 6C_CLAMP
R_SN
=
1–



1
V_OUT
V_IN(MIN)
•
N_P
N_S



L_MAG
C_CLAMP
Be careful to account for the effect of voltage coefficient for
both C_SN and C_CLAMP to ensure that the above relationship
is maintained. In addition to dampening the resonance of
the active clamp, the RC snubber also minimizes the peak
voltage stress seen by the primary-side MOSFETs and
reduces the effect of this LC resonance on the closed-loop
transient response.
Setting the Gate Drive Delay
The active clamp gate driver (AG) and the primary switch
gate driver (PG) switch “in-phase,” with a programmable
overlap time set by the DELAY pin. The PG falling to AG
falling delay (t_DAG) is fixed at 180ns since the timing of
this edge has little impact on efficiency. The AG rising to
PG rising delay (t_DPG) is critical for optimizing efficiency
and must be set in conjunction with the LTC3766 forward
gate and synchronous gate delays. Refer to the LTC3766
data sheet for the procedure to determine the optimal delay
times for a particular application. The primary gate delay
time is set by a resistor from the DELAY pin to ground,
according to the following equation:
( ) ^R_DELAY ⁼
t_DPG – 45ns
• ^1kΩ
9.5ns
In a system where the active clamp is not desired, for
example in a forward converter using resonant reset, this
delay can be set to a minimum by grounding the delay pin.
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