LTC3765_15 Datasheet, PDF (10/24 Pages) Linear Technology – Active Clamp Forward Controller and Gate Driver

LTC3765
OPERATION
The delay time between the primary switch turn-off and the
active clamp turn-on is substantially less critical. Relative
to the power loss due to turning on the primary switch, the
power loss from switching the active clamp is significantly
less. This difference results from both the lower current
that the active clamp switches and the natural resonance
of the system which facilitates zero voltage switching.
When the primary switch turns off, the main transformer
leakage inductance is biased with the peak ripple current
of the inductor reflected through the transformer. This
current drives the voltage across the active clamp PMOS
quickly to 0V. Turning on the PMOS after this transition
results in minimal switching power loss. The LTC3765
active clamp turn on delay is internally fixed to 180ns.
V_IN Undervoltage Lockout
The RUN pin of the LTC3765 has precise thresholds and
programmable hysteresis, which allows it to be used as an
accurate voltage monitor on the input supply. An external
resistive divider from V_IN to the RUN pin ensures that
operation is disabled when V_IN is too low.
Additionally, when the RUN pin is below its threshold, a
5µA current is pulled by the pin. This current, combined
with the external resistive divider, increases the hysteresis
beyond the internal minimum of 4%.
Soft-Start
The SSFLT pin combines a programmable soft-start ramp
for self-starting applications with a fault indicator. If either
the V_CC or the RUN pin voltages are below their thresholds,
the SSFLT pin is internally grounded. When both of these
voltages rise above their thresholds, the SSFLT pin is
released and current flows out of the pin into an external
capacitor. As the capacitor charges from 1V to 3V, the
duty cycle of the gate drivers increases linearly from 0%
to 70%, with a switching frequency set by a resistor from
FSUV to ground. The LTC3766 should begin sending pulses
and take control of the duty cycle before the soft-start pin
reaches 3V; however, if the voltage reaches 3.5V, the linear
regulator turns off to avoid excessive power dissipation in
the linear regulator pass device. With the linear regulator
off, the supply will soon drop below the V_CC falling UVLO
threshold, and the LTC3765 will fault and restart.
Direct Flux Limit
In active clamp forward converters, it is essential to es-
tablish an accurate limit to the transformer flux density
in order to avoid core saturation during load transients or
when starting up into a pre-biased output. Although the
active clamp technique provides a suitable reset voltage
during steady-state operation, the sudden increase in duty
cycle caused in response to a load step can cause the
transformer flux to accumulate or “walk,” potentially lead-
ing to saturation. This occurs because the reset voltage on
the active clamp capacitor cannot keep up with the rapidly
changing duty cycle. This effect is most pronounced at low
input voltage, where the voltage loop demands a greater
increase in duty cycle due to the lower voltage available
to ramp up the current in the output inductor.
Traditionally, transformer core saturation has been avoided
both by limiting the maximum duty cycle of the converter
and by slowing down the loop to limit the rate at which
the duty cycle changes. Limiting the maximum duty cycle
helps the converter avoid saturation for a load step at low
input voltage since the duty cycle maximum is clamped;
however, transformer saturation can also easily occur
at higher input voltage where the maximum duty cycle
clamp is ineffective. Limiting the rate of duty cycle change
in the loop to a point at which the active clamp capacitor
can sufficiently track the change in duty cycle results in
a very poor transient response of the overall converter.
Furthermore, this technique is not guaranteed to prevent
transformer saturation under all operating conditions.
Neither of these traditional techniques will prevent the
transformer from saturating when starting up into a pre-
biased output, where the duty cycle can quickly change
from 0% to 75%.
The LTC3765 and LTC3766 implement a new unique system
for monitoring and directly limiting the flux accumulation
in the transformer core. During a reset cycle, when the ac-
tive clamp PMOS is on, the magnetizing current is directly
measured and limited through a sense resistor in series
with the PMOS source. When the PMOS turns off and
the main NMOS switch turns on, the LTC3765 generates
an accurate internal estimate of the magnetizing current
based on the sensed input voltage on the RUN pin and
transformer core parameters customized to the particular
3765fb
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