LTC3765_15 Datasheet, PDF (17/24 Pages) Linear Technology – Active Clamp Forward Controller and Gate Driver

LTC3765
APPLICATIONS INFORMATION
The above equation assumes that there is no load cur-
rent, which is the worst-case condition for output voltage
rise. If t_OUT is less than t_BIAS, then the soft-start capacitor
value should be increased. Note that these equations are
approximations and the actual times will vary somewhat
with circuit parameters.
Gate Drivers
The active clamp gate driver (AG) and the primary switch
gate driver (PG) are “in-phase,” with a programmable
overlap time set by the DELAY pin. Traditionally in active
clamp drivers, the AG driver must be level-shifted as shown
in the circuit in Figure 7a to drive the active clamp PMOS
gate from approximately V_D to –V_CC + V_D, where V_D is
the forward voltage drop across the Schottky diode D_AG.
A silicon diode can be used instead of a Schottky barrier
diode; however, the forward voltage of the diode does
subtract from the available gate drive of the active clamp
PMOS. This is particularly important at the minimum V_CC
UVLO falling threshold.
The resistor, R_AG, ensures that the active clamp PMOS
is off when not being driven. The active clamp level-shift
circuit components can be chosen with few constraints. The
time constant formed by R_AG and C_AG should be designed
to be substantially longer than the switching period of the
controller. A 0.1µF capacitor for C_AG and a 10k resistor for
R_AG result in a 1ms time constant, which provides suf-
ficient margin for the 75kHz to 500kHz frequency range
available in the LTC3766.
Alternatively, the active clamp PMOS source can be returned
to the V_CC supply bypass capacitor, as shown in Figure 7b.
In this configuration, the level-shift circuit comprised of
C_AG, D_AG and R_AG is not needed. The AG output drives the
gate of the PMOS between V_CC and ground.
V_IN
• • _MAIN
TRANSFORMER
C_AG
AG
R_SN
C_CLAMP
C_SN
PRIMARY
SWITCH
PG
ACTIVE _NMOS
CLAMP
D_AG R_AG
PMOS
I_SMAG
3765 F07a
R_MAG
Figure 7a. Traditional AG and PG Driver Configuration
V_IN
• • _MAIN
TRANSFORMER
R_SN
C_SN
AG
V_CC
C_CLAMP
PRIMARY
SWITCH
ACTIVE _NMOS
CLAMP
PMOS
I_SMAG
R_MAG
PG
3765 F07b
C_VCC
Figure 7b. Alternative AG and PG Driver Configuration
Unlike the configuration in Figure 7a, the main transformer
leakage current spike and magnetizing current return to
the V_CC bypass capacitor. The V_CC capacitor should be
increased to prevent excessive ripple on the supply and
a low impedance plane should be used to route V_CC. The
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3765fb
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