LTC3731_15 Datasheet, PDF (13/34 Pages) Linear Technology – 3-Phase, 600kHz, Synchronous Buck Switching Regulator Controller

LTC3731
OPERATION (Refer to Functional Diagram)
capacitor, the controller will be shut down until the RUN/
SS pin voltage is recycled. This built-in latchoff can be
overridden by providing >5µA at a compliance of 3.8V
to the RUN/SS pin. This additional current shortens the
soft-start period but prevents net discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
condition. Foldback current limiting is activated when the
output voltage falls below 70% of its nominal level whether
or not the short-circuit latchoff circuit is enabled. Foldback
current limit can be overridden by clamping the EAIN pin
such that the voltage is held above the (70%)(0.6V) or
0.42V level even when the actual output voltage is low. Up
to 100µA of input current can safely be accommodated
by the RUN/SS pin.
Input Undervoltage Reset
The RUN/SS capacitor will be reset if the input voltage
(V_CC) is allowed to fall below approximately 4V. The
capacitor on the RUN/SS pin will be discharged until
the short-circuit arming latch is disarmed. The RUN/SS
capacitor will attempt to cycle through a normal soft-start
ramp up after the V_CC supply rises above 4V. This circuit
prevents power supply latchoff in the event of input power
switching break-before-make situations. The PGOOD pin
is held low during start-up until the RUN/SS capacitor
rises above the short-circuit latchoff arming threshold of
approximately 3.8V.
APPLICATIONS INFORMATION
The basic application circuit is shown in Figure 1 on the
first page of this data sheet. External component selection
is driven by the load requirement, and normally begins
with the selection of an inductance value based upon the
desired operating frequency, inductor current and output
voltage ripple requirements. Once the inductors and op-
erating frequency have been chosen, the current sensing
resistors can be calculated. Next, the power MOSFETs and
Schottky diodes are selected. Finally, C_IN and C_OUT are
selected according to the voltage ripple requirements. The
circuit shown in Figure 1 can be configured for operation
up to a MOSFET supply voltage of 28V (limited by the
external MOSFETs and possibly the minimum on-time).
Operating Frequency
The IC uses a constant frequency, phase-lockable ar-
chitecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to the Phase-Locked
Loop and Frequency Synchronization section for additional
information.
A graph for the voltage applied to the PLLFLTR pin versus
frequency is given in Figure 3. As the operating frequency
is increased the gate charge losses will be higher, reducing
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0
0.5
1
1.5
2
2.5
PLLFLTR PIN VOLTAGE (V)
3731 F03
Figure 3. Operating Frequency vs V_PLLFLTR
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 680kHz.
Inductor Value Calculation and Output Ripple Current
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge and transition losses. In addition to
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