LTC3731_15 Datasheet, PDF (12/34 Pages) Linear Technology – 3-Phase, 600kHz, Synchronous Buck Switching Regulator Controller

LTC3731
OPERATION (Refer to Functional Diagram)
C) Continuous Current Operation
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, the controller will
cause current to flow back into the input filter capaci-
tor. If large enough, the input capacitor will prevent the
input supply from boosting to unacceptably high levels.
See C_IN/C_OUT Selection in the Applications Information
section.
Frequency Synchronization
The phase-locked loop allows the internal oscillator to be
synchronized to an external source using the PLLIN pin.
The output of the phase detector at the PLLFLTR pin is
also the DC frequency control input of the oscillator, which
operates over a 250kHz to 600kHz range corresponding
to a voltage input from 0V to 2.4V. When locked, the PLL
aligns the turn on of the top MOSFET to the rising edge of
the synchronizing signal. When no frequency information
is supplied to the PLLIN pin, PLLFLTR goes low, forcing
the oscillator to minimum frequency. A DC source can be
applied to the PLLFLTR pin to externally set the desired
operating frequency. A discharge current of approximately
20µA will be present at the pin with no PLLIN input signal.
Input capacitance ESR requirements and efficiency losses
are reduced substantially in a multiphase architecture
because the peak current drawn from the input capacitor
is effectively divided by the number of phases used and
power loss is proportional to the RMS current squared. A
3-stage, single output voltage implementation can reduce
input path power loss by 90%.
Differential Amplifier
This amplifier provides true differential output voltage
sensing. Sensing both V_OUT+ and V_OUT– benefits regulation
in high current applications and/or applications having
electrical interconnection losses. This sensing also isolates
the physical power ground from the physical signal ground
preventing the possibility of troublesome “ground loops”
on the PC layout and prevents voltage errors caused by
board-to-board interconnects, particularly helpful in VRM
designs.
Power Good
The PGOOD pin is connected to the drain of an internal
N‑channel MOSFET. The MOSFET is turned on once an
internal delay of about 100µs has elapsed and the output
voltage has been away from its nominal value by greater
than 10%. If the output returns to normal prior to the delay
timeout, the timer is reset. There is no delay time for the
rising of the PGOOD output once the output voltage is
within the ±10% “window.”
Phase Mode
The PHASMD pin determines the phase shift between
the rising edge of the TG1 output and the rising edge of
the CLKOUT signal. Grounding the pin will result in 30
degrees phase shift and tying the pin to V_CC will result
in 60 degrees. These phase shift values enable extension
to 6- and 12-phase systems. The PGOOD function above
and the PHASMD function are tied to a common pin in
the UH package.
Undervoltage Shutdown Adjust
The voltage applied to the UVADJ pin is compared to the
internal 1.2V reference to have an externally programmable
undervoltage shutdown. The RUN/SS pin is internally held
low until the voltage applied to the UVADJ pin exceeds
the 1.2V threshold.
Short-Circuit Detection
The RUN/SS capacitor is used initially to turn on and limit
the inrush current from the input power source. Once the
controllers have been given time, as determined by the
capacitor on the RUN/SS pin, to charge up the output
capacitors and provide full load current, the RUN/SS
capacitor is then used as a short-circuit timeout circuit.
If the output voltage falls to less than 70% of its nominal
output voltage, the RUN/SS capacitor begins discharging,
assuming that the output is in a severe overcurrent and/
or short-circuit condition. If the condition lasts for a long
enough period, as determined by the size of the RUN/SS
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