LTC3731_15 Datasheet, PDF (10/34 Pages) Linear Technology – 3-Phase, 600kHz, Synchronous Buck Switching Regulator Controller

LTC3731
PIN FUNCTIONS
V_CC: Main Supply Pin. This pin supplies the controller
circuit power. In the LTC3731 UH package, it also supplies
the high power pulses to drive the external MOSFET gates.
This pin needs to be very carefully and closely decoupled
to the IC’s PGND pin.
VDR: (LTC3731G Package Only) Supplies power to the
bottom gate drivers only. This pin needs to be very care-
fully and closely decoupled to the IC’s PGND pin.
FUNCTIONAL DIAGRAM
PLLIN
F_IN
50k
R_LP ^PLLFLTR
C_LP
CLKOUT
PHASMD**
PHASE DET
OSCILLATOR
CLK1
CLK2
CLK3
PGOOD**
100µs
DELAY
PROTECTION
FCB
+
0.6V ^–
IN^–
40k
IN⁺
40k
DIFFOUT
0.66V
EAIN
0.54V
FCB
40k
–
A1
+
40k
R1
EAIN
V_FB
R2
0.600V
0.660V
I_TH
–
EA
+
+ ^OV
–
C_C
R_C
UVADJ
–
1.2V +
DUPLICATE FOR SECOND AND THIRD
CONTROLLER CHANNELS
RS
LATCH
DROP
OUT
DET
SQ
RQ
0.55V
BOOST
BOT
TG
TOP
FORCE BOT
SWITCH
SW
LOGIC
B
FCB
V_CC (VDR)***
BG
BOT
SHDN
PGND
V_CC
V_IN
D_B
C_B
+
C_IN
I₁ – +
SLOPE
COMP
5(V_FB)
0.86V
SS
CLAMP _2.4V
3mV
54k
–
I₂
+
54k
V_CC
L
36k ^SENSE+
36k ^SENSE–
R_SENSE
C_OUT
V_OUT
FCB
V_CC
1.5µA
6V
SHDN
RST
5(V_FB)
SHED
RUN
SOFT-
START
1.2V
0.600V
INTERNAL
SUPPLY
UV RESET
V_REF
V_CC
SGND*
V_CC
+
C_CC
RUN/SS
C_SS
*THE LTC3731UH USES THE EXPOSED DIE ATTACH PAD FOR THE SGND CONNECTIONS
**THE PHASMD AND PGOOD PIN FUNCTIONS ARE TIED TOGETHER IN THE LTC3731 UH PACKAGE
***LTC3731CG/IG ONLY
Figure 2
10
3731 F02
3731fc