LTC3734 Datasheet, PDF(7/28 Page) Linear Technology – Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

LTC3734 Datasheet, PDF (7/28 Pages) Linear Technology – Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

◁

LTC3734

PI FU CTIO S

VOA+, VOAâ (Pins 1, 2): Inputs to the Internal Operational

Amplifier.

OAOUT (Pin 3): Output of the Internal Operational

Amplifier.

STP_CPUB (Pin 4): Deep Sleep State Input. When the

signal to this pin is low, the voltage regulator enters deep

sleep state and its output voltage is a certain percentage

lower than the VID commands. This offset percentage is

set by the resistor connected to the RDPSLP pin. When the

signal to this pin is high, the voltage regulator exits deep

sleep state.

SGND (Pin 5): Signal Ground. All small-signal compo-

nents and compensation components should connect to

this ground which, in turn, connects to PGND at one point.

SENSE+ (Pin 6): The (+) Input to the Differential Current

Comparator. The ITH pin voltage and built-in offsets be-

tween SENSEâ and SENSE+ pins in conjunction with

RSENSE set the current trip threshold.

SENSEâ (Pin 7): The (â) Input to the Differential Current

Comparator.

RDPRSLP (Pin 8): Deeper Sleep State Resistor Pin. Con-

nect a resistor from this pin to VOA+. This resistor in

conjunction with the RDPSLP resistor sets the output

voltage of the regulator in deeper sleep state.

RDPSLP (Pin 9): Deep Sleep Resistor Pin. Connect a

resistor from this pin to VOA+. This resistor sets the

percentage offset of output voltage in deep sleep state.

RUN/SS (Pin 10): Combination of Soft-Start, Run Control

Input and Short-Circuit Detection Timer. A capacitor to

ground at this pin sets the ramp time to full current output.

Forcing this pin below 1V causes the IC to shut down all

internal circuitry. All functions are disabled in shutdown.

ITH (Pin 11): Error Amplifier Output and Switching Regu-

lator Compensation Point. The current comparatorâs thresh-

old increases with this control voltage. The normal voltage

range of this pin is from 0V to 2.4V

RBOOT (Pin 12): Boot-Up Resistor Pin. Connect a resistor

from this pin to VOA+. This resistor sets the output voltage

during the initial boot-up.

VID0âVID5 (Pins 13, 14, 15, 17, 18, 19): VID Control

Logic Input Pins.

NC (Pin 16): Not Connected.

PGND (Pin 20): Driver Power Ground. Connect to sources

of bottom N-channel MOSFETs and the (â) terminals of CIN.

BG (Pin 21): High Current Gate Drive for Bottom N-Channel

MOSFETs. Voltage swing at this pin is from ground to

PVCC.

PVCC (Pin 22): Power Supply Pin. The on chip gate drivers

are powered from this voltage source. Decouple to PGND

with a minimum of 4.7Î¼F X5R/X7R ceramic capacitor

placed directly adjacent to the IC.

3734f

▷