LTC3734 Datasheet, PDF (16/28 Pages) Linear Technology – Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

LTC3734
APPLICATIO S I FOR ATIO
VID Output Voltage Programming
After 27μs ~ 71μs t_BOOT delay, the output voltage of the
regulator is digitally programmed as defined in Table 1
using the VID0 to VID5 logic input pins. The VID logic
inputs program a precision, 0.25% internal feedback
resistive divider. The LTC3734 has an output voltage
range of 0.700V to 1.708V in 16mV steps.
Refering to the Functional Diagram, there is a resistor,
R_VID, from V_FB to ground. The value of R_VID is controlled
by the six VID input pins. Another internal resistor, 5.33k
(R_ATTEN), completes the resistive divider. The output
voltage is thus set by the ratio of (R_VID + 5.33k) to R_VID.
Each VID digital pin is a high impedance input. Therefore
they must be actively pulled high or pulled low. The logic
low threshold of the VID pins is 0.3V; the logic high
threshold is 0.7V.
Soft-Start/Run Function
The RUN/SS pin provides three functions: 1) run/shut-
down, 2) soft-start and 3) an optional short-circuit latchoff
timer. Soft-start reduces the input power source’s surge
currents by gradually increasing the controller’s current
limit. The latchoff timer prevents very short, extreme load
transients from tripping the overcurrent latch. A small pull-
up current (>5μA) supplied to the RUN/SS pin will prevent
the overcurrent latch from operating. The following para-
graph describes how the functions operate.
An internal 1.5μA current source charges up the soft-start
capacitor, C_SS. When the voltage on RUN/SS reaches
1.5V, the controller is permitted to start operating. As the
voltage on RUN/SS increases from 1.5V to 3.0V, the
internal current limit is increased from 25mV/R_SENSE to
72mV/R_SENSE. The output current thus ramps up slowly,
eliminating the starting surge current required from the
input power supply. If RUN/SS has been pulled all the way
to ground there is a delay before starting of approximately:
( ) ^tDELAY
=
1.5V
1.5μA
C _SS
=
1s/μF
C _SS
The time for the output current to ramp up is then:
( ) ^tIRAMP
=
3V − 1.5V
1.5μA
C _SS
=
1s/μF
C _SS
16
By pulling the RUN/SS pin below 1V the LTC3734 is put
into low current shutdown (I_Q < 100μA). The RUN/SS pin
can be driven directly from logic as shown in Figure 3.
Diode D1 in Figure 3 reduces the start delay but allows
C_SS to ramp up slowly providing the soft-start function.
The RUN/SS pin has an internal 6V zener clamp (see
Functional Diagram).
PV_CC
3.3V OR 5V
RUN/SS
D1
R_SS*
C_SS
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
RUN/SS
C_SS
3734 F03
Figure 3. RUN/SS Pin Interfacing
Start-Up Sequence (Refer to the Functional Diagram)
After soft-start, the output voltage of the regulator settles
at a voltage level equal to V_BOOT.
( ) ^{R2 • R3 + R5}
( ) ^{VBOOT = 0.6V •}
R5 • R1+ R2
By using different R5 resistors, V_BOOT can be programmed.
After the output voltage enters the ±10% regulation win-
dow centered at V_BOOT, the internal power good compara-
tor issues a logic high signal. Refer to the timing diagram
in Figure 4. This signal then enters a logic AND gate, with
MCH_PG being the other input, and the output of the gate
is PG shown in Figure 4. This composite PG signal is then
delayed by t_BOOT amount of time and then becomes MD.
As soon as MD is asserted, the output voltage changes
from V_BOOT to V_VID, a voltage level totally controlled by the
six VID bits. In the LTC3734, the time t_BOOT is set to be 15
switching cycles:
t_BOOT
= 15 ¹
f_S
If f_S is set at 210kHz, t_BOOT = 71μs
If f_S is set at 550kHz, t_BOOT = 27μs
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