LTC3734 Datasheet, PDF (13/28 Pages) Linear Technology – Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

LTC3734
APPLICATIO S I FOR ATIO
Inductor Core Selection
Once the value for L1 is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mμ^® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductor type selected. As inductance increases, core
losses go down. Unfortunately, increased inductance re-
quires more turns of wire and therefore copper losses will
increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
A variety of inductors designed for high current, low
voltage applications are available from manufacturers
such as Sumida, Coilcraft, Coiltronics, Toko and Pana-
sonic.
Power MOSFET, D1 Selection
External power MOSFETs must be selected for output
stage with the LTC3734: one N-channel MOSFET for the
top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
The peak-to-peak drive levels are set by the PV_CC voltage.
This voltage typically ranges from 4.5V to 7V. Conse-
quently, logic-level threshold MOSFETs must be used in
most applications. Pay close attention to the BV_DSS speci-
fication for the MOSFETs as well; most of the logic-level
MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R_DS(ON), gate charge Q_G, reverse transfer ca-
pacitance C_RSS, breakdown voltage BV_DSS and maximum
continuous drain current I_D(MAX).
When the LTC3734 operates at continuous mode in a step-
down configuration, the duty cycles for the top and bottom
MOSFETs are approximately:
Top MOSFET Duty Cycle = ^VOUT
(1)
V_IN
Bottom MOSFET Duty Cycle = ^{VIN – VOUT}
(2)
V_IN
The conduction losses of the top and bottom MOSFETs are
therefore:
( ) ( ) ^P_CONTOP
=
V_OUT
V_IN
•
I_OUT
2_•
1+ δ • ΔT
• R_DS(ON)
(3)
P_CONBOT
=
V_IN
– V_OUT
V_IN
• ₍I_OUT)²
• ₍1+
δ
•
ΔT₎
(4)
• R_DS(ON)
where I_OUT is the maximum output current at full load, ΔT
is the difference between MOSFET operating temperature
and room temperature, and δ is the temperature depen-
dency of R_DS(ON). δ is roughly 0.004/°C ~ 0.006/°C for low
voltage MOSFETs.
The power losses of driving the top and bottom MOSFETs
are simply:
P_DRTOP = Q_G • PV_CC • f
(5)
P_DRBOT = Q_G • PV_CC • f
(6)
Use Q_G data at V_GS = PV_CC in MOSFET data sheets. f is the
switching frequency as described previously. Please no-
tice that the above gate driving losses are usually not
dissipated by the MOSFETs. Instead they are mainly
dissipated on the internal drivers of the LTC3734, if there
are no resistors connected between the drive pins (TG,
BG) and the gates of the MOSFETs.
The calculation of MOSFET switching loss is complicated
by several factors including the wide distribution of power
MOSFET threshold voltage, the nonlinearity of current
rising/falling characteristic and the Miller Effect. Given the
data in a typical power MOSFET data sheet, the switching
losses of the top and bottom MOSFETs can only be
estimated as follows:
Kool Mμ is a registered trademark of Magnetics, Inc.
3734f
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