LTC3734 Datasheet, PDF (24/28 Pages) Linear Technology – Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

LTC3734
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3734. Check the following in your layout:
1) Are the signal and power grounds segregated? Keep the
SGND at one end of a PC board to prevent MOSFET
currents from traveling under the IC. The IC signal ground
pin (Pin 5) should be used to hook up all control circuitry
on one side of the IC, routing the copper through SGND,
under the IC covering the “shadow” of the package,
connecting to the PGND pin (Pin 20) and then continuing
on to the (–) plate of C_OUT.
2) Is the PV_CC decoupling capacitor connected immedi-
ately adjacent to the PV_CC and PGND pins? A 1μF ceramic
capacitor of the X7R or X5R material is small enough to fit
very close to the IC to minimize the ill effects of the large
current pulses drawn to drive the power MOSFETs.
An additional 4.7μF ~ 10μF of ceramic, tantalum or other
low ESR capacitor is recommended in order to keep PV_CC
stable. The power ground returns to the sources of the
bottom N-channel MOSFETs, anodes of the Schottky
diodes, and (–) plates of C_IN, which should have the
shortest trace length possible.
3) Are the SENSE ^– and SENSE ⁺ leads routed together with
minimum PC trace spacing? The filter capacitors between
SENSE ⁺ and SENSE^– pin pairs should be as close as
possible to the LTC3734. Ensure accurate current sensing
with Kelvin connections at the current sense resistor. See
Figure 8.
4) Does the (+) plate of C_IN connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the AC current to the MOSFETs. Keep the input
current path formed by the input capacitor, top and bottom
MOSFETs, and the Schottky diode on the same side of the
PC board in a tight loop to minimize conducted and
radiated EMI.
5) Keep the “noisy” nodes, SW, BOOST, TG and BG away
from sensitive small-signal nodes. Ideally the switch
nodes should be placed at the furthest point from the
LTC3734.
It is critical to keep the high-switching-current paths to a
small physical size. High electric and magnetic fields will
radiate from these “loops” just as radio stations transmit
signals. The output capacitor ground should return to the
negative terminal of the input capacitor and not share a
common ground path with any switched current paths.
The left half of the circuit gives rise to the “noise” gener-
ated by a switching regulator. The ground terminations of
the sychronous MOSFETs and Schottky diodes should
return to the negative plate(s) of the input capacitor(s)
with a short isolated PC trace since very high switched
currents are present. A separate isolated path from the
negative plate(s) of the input capacitor(s) should be used
to tie in the IC power ground pin (PGND) and the signal
ground pin (SGND). This technique keeps inherent signals
generated by high current pulses from taking alternate
current paths that have finite impedances during the total
period of the switching regulator. External OPTI-LOOP
compensation allows overcompensation for PC layouts
which are not optimized but this is not the recommended
design procedure.
PADS OF SENSE RESISTOR
TRACE TO INDUCTOR
TRACE TO OUTPUT CAP (+)
SENSE⁺ SENSE ^–
3734 F08
Figure 8. Proper Current Sense Connections
3734f
24