LTC3734 Datasheet, PDF (14/28 Pages) Linear Technology – Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

LTC3734
APPLICATIO S I FOR ATIO
P_SWTOP
=
V_IN2
•
I_OUT
2
•
f
• C_RSS
• R_DR
•
(7)
⎛
⎝⎜
V_DR
–
1
V_TH(MIN)
+
1^⎞
V_{TH(MIN) ⎠⎟}
P_SWBOT ≈ 0
(8)
where R_DR is the effective driver resistance (of approxi-
mately 2Ω), V_DR is the driving voltage (= PV_CC) and
V_TH(MIN) is the minimum gate threshold voltage of the
MOSFET. Please notice that the switching loss of the
bottom MOSFET is effectively negligible because the cur-
rent conduction of the antiparalleling diode. This effect is
often referred as zero-voltage-transition (ZVT). Similarly
when the LTC3734 converter works under fully synchro-
nous mode at light load, the reverse inductor current can
also go through the body diode of the top MOSFET and
make the turn-on loss to be negligible. However, equa-
tions 7 and 8 have to be used in calculating the worst-case
power loss, which happens at highest load level.
The selection criteria of power MOSFETs start with the
stress check:
V_IN < BV_DSS
I_MAX < I_D(MAX)
and
P_CONTOP + P_SWTOP < top MOSFET maximum power
dissipation specification
P_CONBOT + P_SWBOT < bottom MOSFET maximum power
dissipation specification
The maximum power dissipation allowed for each MOSFET
depends heavily on MOSFET manufacturing and packag-
ing, PCB layout and power supply cooling method.
Maximum power dissipation data are usually specified in
MOSFET data sheets under different PCB mounting
conditions.
The next step of selecting power MOSFETs is to minimize
the overall power loss:
P_OVL = P_TOP + P_BOT
= (P_CONTOP + P_DRTOP + P_SWTOP) + (P_CONBOT +
P_DRBOT + P_SWBOT)
14
For typical mobile CPU applications where the ratio be-
tween input and output voltages is higher than 2:1, the
bottom MOSFET conducts load current most of the time
while the main losses of the top MOSFET are for switching
and driving. Therefore a low R_DS(ON) part (or multiple parts
in parallel) would minimize the conduction loss of the
bottom MOSFET while a higher R_DS(ON) but lower Q_G and
C_RSS part would be desirable for the top MOSFET.
The Schottky diode, D1 in Figure 1, conducts during the
dead-time between the conduction of the top and bottom
MOSFETs. This helps reduce the current flowing through
the body diode of the bottom MOSFET. A body diode
usually has a forward conduction voltage higher than that
of a Schottky and is thus detrimental to efficiency. The
charge storage and reverse recovery of a body diode also
cause high frequency rings at the switching nodes (the
conjunction nodes between the top and bottom MOSFETs),
which are again not desired for efficiency or EMI. Some
power MOSFET manufacturers integrate a Schottky diode
with a power MOSFET, eliminating the need to parallel an
external Schottky. These integrated Schottky-MOSFETs,
however, have smaller MOSFET die sizes than conven-
tional parts and are thus not suitable for high current
applications.
C_IN and C_OUT Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V_OUT/
V_IN. A low ESR input capacitor sized for the maximum
RMS current must be used. The RMS input ripple current
is estimated to be:
I_RMS
≅
I_OUT(MAX)
V_OUT
V_IN
V_{IN − 1}
V_OUT
This formula has a maximum at V_IN = 2V_OUT, where
I_RMS = I_OUT(MAX)/2
This simple worst-case condition is commonly used for
design, considering input/output variations and long
term reliability. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
3734f