GM71C4403C Datasheet, PDF (8/10 Pages) LG Semicon Co.,Ltd. – 1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM

LG Semicon
GM71C4403C
Notes:
1. AC measurements assume tT = 2ns.
2. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
3. Measured with a lode circuit equivalent to 1 TTL loads and 100 pF.
4. Assumes that tRCD>=tRCD(max) and tRAD<=tRAD(max).
5. Assumes that tRCD<=tRCD(max) and tRAD>=tRAD(max).
6. ^{tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the output achieves the}
open circuit condition and is not referenced to output voltage levels.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.Also transition
times are measured between VIH and VIL.
8. Operation with the tRCD(max) limit insures that tRAC(max) can be met tRCD(max) is specified as a
reference point only: if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
9. Operation with the tRAD(max) limit insures that tRAC(max) can be met tRAD(max) is specified as a
reference point only: if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
10. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only if tWCS >=tWCS(min), the cycle is an early write cycle and
the data out pin will remain open circuit (high impedance) throughout the entire cycle if
tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a read-
modify-write and the data output will contain data read from the selected cell if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or a read modify write cycle.
12. tRASP defines RAS pulse width in extended data out mode cycles.
13. Access time is determined by the longest among tAA, tCAC and tACP.
14. An initial pause of 100us is required after power up followed by a minimum of eight
initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal
refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required.
15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
16. Test mode operation specified in this data sheet is 2bits test function controlled by control
address bit CA0. This test mode operation can be performed by WE-and-CAS-before-RAS
(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read
cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the
condition of the output data is low level. In order to end this test mode operation, perform RAS
only refresh cycle or a CAS-before-RAS refresh cycle.
17. In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2ns to 5ns for
the specified value. These parameters should be specified in test mode cycles by adding the
above value to the specified value in this data sheet.
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