GM71C4403C Datasheet, PDF (4/10 Pages) LG Semicon Co.,Ltd. – 1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM

LG Semicon
GM71C4403C
Capacitance (VCC = 5V+/-10%, TA = 25C)
Symbol
Parameter
Min
Max Unit
Note
CI1
Input Capacitance (Address)
-
5
§Ü
1
CI2
Input Capacitance (Clocks)
-
7
§Ü
1
CI/O
Data Input/Output Capacitance (Data-In/Out) -
7
§Ü
1, 2
¤
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT.
AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 14, 15, 16)
Test Conditions
Input level : VIL=0V, VIH=3.0V
Input rise and fall times: 2ns
Input timing reference levels: VIL=0.8V, VIH=2.4V
Output timing reference levels: VOL=0.8V, VOH=2.0V
Output load : 1 TTL gate + CL (100§Ü)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol
Parameter
GM71C4403 GM71C4403 GM71C4403
C-60
C-70
C-80
Min Max Min Max Min Max
Unit
Note
tRC
Random Read or Write Cycle Time
104 - 124 - 144 - ns
tRP
RAS Precharge Time
40 - 50 - 60 - ns
tRAS
RAS Pulse Width
60 10,000 70 10,000 80 10,000 ns
19
tCAS
CAS Pulse Width
10 10,000 13 10,000 15 10,000 ns
20
tASR
Row Address Set-up Time
0 - 0 - 0 - ns
tRAH
Row Address Hold Time
10 - 10 - 10 - ns
tASC
Column Address Set-up Time
0 - 0 - 0 - ns
tCAH
Column Address Hold Time
10 - 13 - 15 - ns
tRCD
RAS to CAS Delay Time
20 45 20 52 20 60 ns
8
tRAD
RAS to Column Address Delay Time
15 30 15 35 15 40 ns
9
tRSH
RAS Hold Time
15 - 18 - 20 - ns
tCSH
CAS Hold Time
48 - 58 - 68 - ns 22
tCRP
CAS to RAS Precharge Time
10 - 10 - 10 - ns
tODD
OE to DIN Delay Time
15 - 18 - 20 - ns
tDZO
OE Delay Time from DIN
0 - 0 - 0 - ns
tDZC
CAS Set-up Time from DIN
0 - 0 - 0 - ns
tT
Transition Time (Rise and Fall)
2 50 2 50 2 50 ns
7
tREF
Refresh Period
- 16 - 16 - 16 ms
4