2032VE Datasheet, PDF (9/14 Pages) Lattice Semiconductor – 3.3V In-System Programmable High Density SuperFAST™ PLD

ispLSI 2032VE Timing Model
Specifications ispLSI 2032VE
I/O Cell
Ded. In
I/O Pin
(Input)
#21
I/O Delay
#20
Reset
GRP
GRP
#22
#45
GLB
Feedback
Comb 4 PT Bypass #23
Reg 4 PT Bypass
#24
GLB Reg Bypass
#28
20 PT
XOR Delays
#25, 26, 27
GLB Reg
Delay
D
Q
RST
#29, 30,
31, 32
ORP
I/O Cell
ORP Bypass
#37
ORP
Delay
#36
#38,
39
I/O Pin
(Output)
Y0,1,2
GOE 0
#43, 44
#42
Control _RE
PTs
OE
#33, 34, CK
35
Derivations of tsu, th and tco from the Product Term Clock
tsu
= Logic + Reg su - Clock (min)
= (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
2.5ns = (0.6 + 0.7 + 2.2) + (6.8) - (0.6 + 0.7 + 0.5)
th
= Clock (max) + Reg h - Logic
= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
2.3ns = (0.6 + 0.7 + 2.8) + (1.7) - (0.6 + 0.7 + 2.2)
tco
= Clock (max) + Reg co + Output
= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #22 + #35) + (#31) + (#36 + #38)
7.3ns = (0.6 + 0.7 + 2.8) + (0.7) + (1.3 + 1.2)
Note: Calculations are based on timing specifications for the ispLSI 2032VE-225L.
Table 2-0042/2032VE
#40, 41
0491/2032VE
9