2032VE Datasheet, PDF (13/14 Pages) Lattice Semiconductor – 3.3V In-System Programmable High Density SuperFAST™ PLD

Pin Configuration
ispLSI 2032VE 48-Pin TQFP Pinout Diagram
Specifications ispLSI 2032VE
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
BSCAN
1_{TDI/IN 0}
I/O 0
I/O 1
I/O 2
2_NC
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
ispLSI 2032VE 31
7
Top View
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
NC²
I/O 18
I/O 17
I/O 16
TMS/NC²
RESET/Y1¹
VCC
TCK/Y2¹
I/O 15
I/O 14
I/O 13
I/O 12
48TQFP/2032VE
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, V_CC or GND.
Signal Configuration
ispLSI 2032VE 49-Ball caBGA Signal Diagram
7654321
A
NC¹
I/O
21
I/O GOE I/O
23
0
25
I/O
NC¹
27
A
B
I/O I/O I/O I/O I/O I/O I/O
18
17
20
22
24
26
30
B
C
I/O
16
TMS/
NC¹
I/O
19
GND
I/O
28
I/O
29
Y0
C
D
RESET/
I/O
Y1
15
VCC NC¹ VCC
I/O
31
BSCAN
D
E
TCK/ I/O
Y2
13
I/O
12
GND
I/O
3
TDI/ I/O
IN0
0
E
F
I/O I/O I/O I/O I/O I/O I/O
14
10
8
6
4
1
2
F
G
NC¹
I/O
11
I/O TDO/ I/O
9
IN1
7
I/O
NC¹
5
G
ispLSI 2032VE
Bottom View
7
6
5
4
3
2
1
49-BGA/2032VE
1. NCs are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
13