2032VE Datasheet, PDF (10/14 Pages) Lattice Semiconductor – 3.3V In-System Programmable High Density SuperFAST™ PLD

Specifications ispLSI 2032VE
Power Consumption
Power consumption in the ispLSI 2032VE device de- used. Figure 3 shows the relationship between power
pends on two primary factors: the speed at which the and operating speed.
device is operating and the number of product terms
Figure 3. Typical Device Power Consumption vs fmax
150
125
100
ispLSI 2032VE-225
75
ispLSI 2032VE-180
and slower
50
25
0
25
50 75 100 125 150 175 200 225
fmax (MHz)
Notes: Configuration of two 16-bit counters
Typical current at 3.3V, 25° C
ICC can be estimated for the ispLSI 2032VE using the following equation:
For ispLSI 2032VE-225: ICC(mA) = 4.5 + (# of PTs * 1.29) + (# of nets * Max freq * 0.0068)
For ispLSI 2032VE-180 and slower: ICC(mA) = 4.5 + (# of PTs * 1.05) + (# of nets * Max freq * 0.0068)
Where:
# of PTs = Number of product terms used in design
# of nets = Number of signals used in device
Max freq = Highest clock frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two
GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to
operating conditions and the program in the device, the actual ICC should be verified.
0127A/2032VE
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