80VA Datasheet, PDF(4/27 Page) Lattice Semiconductor – In-System Programmable 3.3V Generic Digital CrosspointTM

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80VA Datasheet, PDF (4/27 Pages) Lattice Semiconductor – In-System Programmable 3.3V Generic Digital CrosspointTM

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Specifications ispGDX80VA

I/O MUX Operation

MUX1

MUX0

Data Input Selected

allow adjacent I/O cell outputs to be directly connected

without passing through the global routing pool. The

relationship between the [N+i] adjacent cells and A, B, C

and D inputs will vary depending on where the I/O cell is

located on the physical die. The I/O cells can be grouped

into ânormalâ and âreflectedâ I/O cells or I/O âhemi-

spheres.â These are defined as:

Flexible mapping of MUXselx to MUXx allows the user to

change the MUX select assignment after the ispGDXVA

device has been soldered to the board. Figure 1 shows

that the I/O cell can accept (by programming the appro-

priate fuses) inputs from the MUX outputs of four adjacent

I/O cells, two above and two below. This enables cascad-

ing of the MUXes to enable wider (up to 16:1) MUX

implementations.

The I/O cell also includes a programmable flow-through

latch or register that can be placed in the input or output

path and bypassed for combinatorial outputs. As shown

in Figure 1, when the input control MUX of the register/

latch selects the âAâ path, the register/latch gets its inputs

from the 4:1 MUX and drives the I/O output. When

selecting the âBâ path, the register/latch is directly driven

by the I/O input while its output feeds the GRP. The

programmable polarity Clock to the latch or register can

be connected to any I/O in the I/O-CLK/CLKEN set (one-

quarter of total I/Os) or to one of the dedicated clock input

pins (Yx). The programmable polarity Clock Enable input

to the register can be programmed to connect to any of

the I/O-CLK/CLKEN input pin set or to the global clock

enable inputs (CLKENx). Use of the dedicated clock

inputs gives minimum clock-to-output delays and mini-

mizes delay variation with fanout. Combinatorial output

mode may be implemented by a dedicated architecture

bit and bypass MUX. I/O cell output polarity can be

programmed as active high or active low.

Device

Normal I/O Cells

ispGDX80VA

B9-B0, A19-A0,

D19-D10

ispGDX160V/VA B19-B0, A39-A0,

D39-D20

ispGDX240VA

B29-B0, A59-A0,

D59-D30

Reflected I/O Cells

B10-B19, C0-C19,

D0-D9

B20-B39, C0-C39,

D0-D19

B30-B59, C0-C59,

D0-D29

Table 2 shows the relationship between adjacent I/O

cells as well as their relationship to direct MUX inputs.

Note that the MUX expansion is circular and that I/O cell

B10, for example, draws on I/Os B9 and B8, as well as

B11 and B12, even though they are in different hemi-

spheres of the physical die. Table 2 shows some typical

cases and all boundary cases. All other cells can be

extrapolated from the pattern shown in the table.

Figure 2. I/O Hemisphere Configuration of

ispGDX80VA

D19

I/O cell 0 I/O cell 79

D10 D9

MUX Expander Using Adjacent I/O Cells

The ispGDXVA allows adjacent I/O cell MUXes to be

cascaded to form wider input MUXes (up to 16 x 1)

without incurring an additional full Tpd penalty. However,

there are certain dependencies on the locality of the

adjacent MUXes when used along with direct MUX

inputs.

B9 B10

B19

I/O cell 39 I/O cell 40

Adjacent I/O Cells

Direct and Expander Input Routing

Expansion inputs MUXOUT[n-2], MUXOUT[n-1],

MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable

for each I/O cell MUX. These expansion inputs share the

same path as the standard A, B, C and D MUX inputs, and

Table 2 also illustrates the routing of MUX direct inputs

that are accessible when using adjacent I/O cells as

inputs. Take I/O cell D13 as an example, which is also

shown in Figure 3.

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