80VA Datasheet, PDF (3/27 Pages) Lattice Semiconductor – In-System Programmable 3.3V Generic Digital CrosspointTM

Specifications ispGDX80VA
Architecture
The ispGDXVA architecture is different from traditional
PLD architectures, in keeping with its unique application
focus. The block diagram is shown below. The program-
mable interconnect consists of a single Global Routing
Pool (GRP). Unlike ispLSI devices, there are no pro-
grammable logic arrays on the device. Control signals for
OEs, Clocks/Clock Enables and MUX Controls must
come from designated sets of I/O pins. The polarity of
these signals can be independently programmed in each
I/O cell.
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
In-system programming is accomplished through the
standard Boundary Scan protocol.
The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped
together with one group per side.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines as well as a 4x4 crossbar switch con-
trolled by software for increased routing flexiability (Figure
1). The four data inputs to the MUX (called M0, M1, M2,
and M3) come from I/O signals in the GRP and/or
adjacent I/O cells. Each MUX data input can access one
quarter of the total I/Os. For example, in an 80-I/O
ispGDXVA, each data input can connect to one of 20 I/O
pins. MUX0 and MUX1 can be driven by designated I/O
pins called MUXsel1 and MUXsel2. Each MUXsel input
covers 25% of the total I/O pins (e.g. 20 out of 80). MUX0
and MUX1 can be driven from either MUXsel1 or MUXsel2.
Figure 1. ispGDXVA I/O Cell and GRP Detail (80 I/O Device)
Logic “0” Logic “1”
80 I/O Inputs
I/OCell 0
I/O Cell 79
I/O Cell 1
••
•••
•
E²CMOS
Programmable
Interconnect
I/O Group A
I/O Group B
I/O Group C
I/O Group D
I/O Cell 78
•••
From MUX Outputs
of 2 Adjacent I/O Cells
N+2
N+1
4x4
Crossbar
Switch
N-1
N-2
To 2 Adjacent
I/O Cells above
Bypass Option
4-to-1 MUX
M0
M1
M2
M3
MUX0 MUX1
Register
or Latch
A
C
BD
QR
CLK
Prog. ^Prog.
Pull-up ^{Bus Hold}
(VCCIO) ^Latch
I/O
Pin
Prog. Open Drain
From MUX Outputs
of 2 Adjacent I/O Cells
To 2 Adjacent
I/O Cells below
CLK_EN Reset
2.5V/3.3V Output
Prog. Slew Rate
Boundary
Scan Cell
I/O Cell 38
I/O Cell 39
40 I/O Cells
••••••
80 Input GRP
Inputs Vertical
Outputs Horizontal
Global
Y0-Y3
Global
Reset
Clocks /
Clock_Enables
•••
I/O Cell 41
40 I/O Cells
I/O Cell 40
ispGDXVA architecture enhancements over ispGDX (5V)
3
I/O Cell N