80VA Datasheet, PDF (12/27 Pages) Lattice Semiconductor – In-System Programmable 3.3V Generic Digital CrosspointTM

Specifications ispGDX80VA
External Timing Parameters
Over Recommended Operating Conditions
TEST¹
PARAMETER COND. #
DESCRIPTION
-7
-9
UNITS
MIN. MAX. MIN. MAX.
tpd²
A 1 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)
– 7.0 – 9.0 ns
tsel²
A 2 Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
– 7.0 – 9.0 ns
fmax (Tog.) – 3 Clock Frequency, Max. Toggle
100 – 83 – MHz
fmax (Ext.)
–
4
Clock Frequency with External Feedback ⁽
1
tsu3+tgco1
)
80 – 62.5 – MHz
tsu1
tsu2
– 5 Input Latch or Register Setup Time Before Y_x
– 6 Input Latch or Register Setup Time Before I/O Clock
5.5 – 7.0 – ns
4.5 – 6.0 – ns
tsu3
tsu4
– 7 Output Latch or Register Setup Time Before Y_x
– 8 Output Latch or Register Setup Time Before I/O Clock
5.5 – 7.0 – ns
4.5 – 6.0 – ns
tsuce1
tsuce2
– 9 Global Clock Enable Setup Time Before Y_x
– 10 Global Clock Enable Setup Time Before I/O Clock
3.5 – 4.0 – ns
2.5 – 3.0 – ns
tsuce3
th1
th2
– 11 I/O Clock Enable Setup Time Before Y_x
– 12 Input Latch or Reg. Hold Time (Y_x)
– 13 Input Latch or Reg. Hold Time (I/O Clock)
6.5 – 8.5 – ns
0.0 – 0.0 – ns
2.5 – 3.0 – ns
th3
– 14 Output Latch or Reg. Hold Time (Y_x)
th4
– 15 Output Latch or Reg. Hold Time (I/O Clock)
0.0 – 0.0 – ns
2.5 – 3.0 – ns
thce1
thce2
– 16 Global Clock Enable Hold Time (Y_x)
– 17 Global Clock Enable Hold Time (I/O Clock)
0.0 – 0.0 – ns
2.5 – 3.0 – ns
thce3
tgco1²
tgco2²
tco1²
– 18 I/O Clock Enable Hold Time (Y_x)
A 19 Output Latch or Reg. Clock (from Y_x) to Output Delay
A 20 Input Latch or Register Clock (from Y_x) to Output Delay
A 21 Output Latch or Register Clock (from I/O pin) to Output Delay
0.0 – 0.0 – ns
– 7.0 – 9.0 ns
– 11.0 – 13.5 ns
– 9.0 – 11.5 ns
tco2²
A 22 Input Latch or Register Clock (from I/O pin) to Output Delay
– 13.0 – 15.7 ns
ten²
B 23 Input to Output Enable
– 8.5 – 10.5 ns
tdis²
C 24 Input to Output Disable
– 8.5 – 10.5 ns
ttoeen²
B 25 Test OE Output Enable
– 8.5 – 10.5 ns
ttoedis²
C 26 Test OE Output Disable
– 8.5 – 10.5 ns
twh
– 27 Clock Pulse Duration, High
5.0 – 6.0 – ns
twl
– 28 Clock Pulse Duration, Low
5.0 – 6.0 – ns
trst
– 29 Register Reset Delay from RESET Low
– 18.0 – 22.0 ns
trw
– 30 Reset Pulse Width
14.0 – 18.0 – ns
tsl
D 31 Output Delay Adder for Output Timings Using Slow Slew Rate
– 7.0 – 9.0 ns
tsk
A 32 Output Skew (tgco1 Across Chip)
– 0.5 – 1.0 ns
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
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