ML7345 Datasheet, PDF (216/261 Pages) –

FEDL7345/D-02
ML7345/ML7345D
0x7B[TX_PKT_LEN_L]
Function: TX packet length setting (low byte)
Address:0x7B (BANK0)
Reset value:0x00
Bit
Bit name
7:0 TX_PKT_LEN[7:0]
Reset value
0000_0000
R/W
Description
R/W
TX packet length setting (low byte)
For details, please refer to [PKT_LEN_H: B0 0x7A] register.
0x7C[WR_TX_FIFO]
Function: TX FIFO
Address:0x7C (BANK0)
Reset value:0x00
Bit
Bit name
7:0 TX_FIFO[7:0]
Reset value
0000_0000
R/W
Description
TX FIFO
(Note) TX data strored in the TX FIFO is one packet, regardless of packet
length. If one packet is stored - (after generation of TX data request
acceptance completion interrupt (INT[17] (group 3) and before generation
W
of TX completion interrupt, INT16 (group3) ) - and if the next writing access
is atempted, the TX FIFO will be over-wrtten. And TX FIFO access error
interrupt, INT[20] (group3) will be generated. In case of TX FIFO access
error occurs, set STATE_CLR0([STATE_CLR: B0 0x16(0)]) = 0b1. (TX
FIFO pointer clear)
For details, plese refer to the “FIFO control function”.
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