ML7345 Datasheet, PDF (21/261 Pages) –

FEDL7345/D-02
ML7345/ML7345D
●SPI Interface Characteristics
ML7345/ML7345D
Item
SCLK clock frequency
SCEN input setup time
SCEN input hold time
SCLK high pulse width
SCLK low pulse width
SDI input setup time
SDI input hold time
SCEN negate period
SDO output delay time
Symbol
Condition
Min
Typ
Max
Unit
FSCLK
0.032
2
16
MHz
TSCENSU
30
−
−
ns
TSCENH
30
−
−
ns
TSCLKH
28
−
−
ns
Load
TSCLKL
capacitance
28
−
−
ns
TSDISU
CL = 20pF
5
−
−
ns
TSDIH
15
−
−
ns
TSCENNI
200
−
−
ns
TSDODLY
−
−
22
ns
(Note) All measurement condition for the timings are VDDIO * 20% level and VDDIO * 80% level.
SCEN
SCLK
SDI
SDO
TSCENSU
FSCLK
TSCLKH
TSCLKL
TSDISU TSDIH
MSB IN
BITS6-1
TSDODLY
MSB OUT
BITS6-1
TSCENH
LSB IN
LSB OUT
SCEN
TSCENNI
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