ML7345 Datasheet, PDF (119/261 Pages) –

FEDL7345/D-02
ML7345/ML7345D
(3) FIFO mode (65bytes or more)
The Host must write TX data to the TX_FIFO while checking INT[5] (group1: FIFO-Full interrupt) and INT[4] (group1:
FIFO-Empty interrupt) in order to avoid FIFO-Overrun or FIFO-Underrun. Other operations are identical to the FIFO mode
(less than 64bytes). Enabling FAST_TX mode by FAST_TX_EN ([RF_STATUS_CTRL: B0 0x0A(5)] = 0b1, TX will start
when data amount written to the FIFO exceeds the bytes+1 in the [TXFIFO_THRL: B0 0x18].
START
FAST_TX mode setting
[RF_STATUS_CTRL: B0 0x0A]
TX FIFO-Full level setting [TXFIFO_THRH: B0 0x17]
TX FIFO-Empty level setting [TXFIFO_THRL: B0 0x18]
Write TX data
[WR_TX_FIFO:B0 0x7C]
●If data written to FIFO exceed THFIFO_THRL[5:0]
[TXFIFO_THRL:B0 0x18(5-0)]+1, ()TX will start.
●Please refer to RF state transition wait flow.
FIFO-Empty (INT[4])?
([INT_SOURCE_GRP1: B0 0x0D(4)])
No
Yes
INT[4] clear
([INT_SOURCE_GRP: B0 0x0D)
TX FIFO-Empty level
Disable setting
[TX_FIFO_THRL: B0 0x18]
Write TX data
[WR_TX_FIFO:B0 0x7C]
*Total data amount should be the size
subtracting CRC length from the
Length value.
If too much TX data written to a
FIFO, after TX completion interrupt,
issue TRX_OFF and TX FIFO must
be cleared.
TX Data request accept
No
completion (INT[17])?
([INT_SOURCE_GRP3: B0 0x0F(1)])
TX FIFO-Empty level
Enable setting
[TX_FIFO_THRL: B0 0x18]
Yes
No
TX completion (INT[16])?
([INT_SOURCE_GRP3: B0 0x0F(0)])
Yes
INT[16] and INT[17] clear
([INT_SOURCE_GRP3: B0 0x0F])
Write TX data
[WR_TX_FIFO:B0 0x7C]
Yes
Set RX_ON after TX completion?
Yes
[RF_STATUS_CTRL:B0 0x0A]
No
Yes
Set TRX_OFF/SLEEP after TX?
[RF_STATUS_CTRL:B0 0x0A]
No
Yes
RX?
No
Next packet TX?
No
To RF state transition wait flow
RX_ON issue
[RF_STATUS: B0 0x0B]
To RF state transition wait and
RX flow
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