ML7345 Datasheet, PDF (203/261 Pages) –

FEDL7345/D-02
ML7345/ML7345D
0x5C[IQ_PHASE_ADJ_H]
Function: IF IQ phase balance adjustment (high 3bits)
Address: 0x5C (BANK0)
Reset value: 0x00
Bit
Bit name
7:5 Reserved
4 IQ_PHASE_ADJ_SIGN
3 Reserved
2:0 IQ_PHASE_ADJ[10:8]
Reset value
000
0
0
000
R/W
Description
R/W
IQ signal phase adjustment sign bit
R/W
0: Plus
1: Minus
R/W
IQ signal phase adjustment setting (high 3bits)
* Combined with 8bits of the [IQ_PHASE_ADJ_L:B0 0x5D] register, this is
calculated using a total of 11bits.
bit10: 1/2
bit9 : 1/4
bit8 : 1/8
R/W
bit7 : 1/16
bit6 : 1/32
bit5 : 1/64
bit4 : 1/128
bit3 : 1/256
bit2 : 1/512
bit1 : 1/1024
bit0 : 1/2048
[Description]
1. Image rejection can be adjusted by IQ_PHASE_ADJ [10:0] and IQ_PHASE_ADJ_SIGN. For details, please refer to the
“I/Q Adjustment”.
0x5D[IQ_PHASE_ADJ_L]
Function: IF IQ phase balance adjustment (low byte)
Address: 0x5D (BANK0)
Reset value: 0x00
Bit
Bit name
7:0 IQ_PHASE_ADJ[7:0]
Reset value
0000_0000
R/W
Description
IQ signal phase adjustment setting (low byte)
R/W * Combined with 3bits of [IQ_PHASE_ADJ_H:B0 0x5C] register, this is
calculated using a total of 11bits.
[Description]
1. Image rejection can be adjusted by IQ_PHASE_ADJ [10:0] and IQ_PHASE_ADJ_SIGN. For details, please refer to the
“I/Q Adjustment”.
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