ML7345 Datasheet, PDF (190/261 Pages) –

FEDL7345/D-02
ML7345/ML7345D
0x3A[ED_RSLT]
Function: ED value indication
Address:0x3A (BANK0)
Reset value:0x00
Bit
Bit name
7:0 ED_VALUE[7:0]
Reset value
0000_0000
R/W
Description
ED value indication
(Note) If ED_RSLT_SET([ED_CTRL: B0 0x41(3)]) = 0b0, ED value is
R
updated constantly during RX_ON. If ED_RSLT_SET = 0b1, ED value is
acquired at SyncWord detection timing. The value is updated at reading
RX_FIFO.
[Description]
1. For details of ED value acquisition operation, please refer to the “Energy detection value (ED value) acquisition
function”
0x3B[IDLE_WAIT_H]
Function: IDLE detection period setting during CCA (high 2bits)
Address:0x3B (BANK0)
Reset value:0x00
Bit
Bit name
7:2 Reserved
1:0 IDLE_WAIT[9:8]
Reset value
00_0000
00
R/W
Description
R/W
IDLE judgement max. wait time setting (high 2bits)
(Note) In CCA IDLE judgement, it is used for detecting long IDLE (no carrier)
period.
(Note)Combined toghether with [IDLE_WAIT_L:B0 0x3C] register. IDLE
R/W
detection period is programmed as follows.
IDLE detection period =
ED value averaging period (default 8 times = 128μs) + (IDLE_WAIT[9:0] *
16μs)
[Description]
1. For details operation of CCA, please refer to the “CCA(Clear Channel Asessment) function”.
0x3C[IDLE_WAIT_L]
Function: IDLE detection period setting during CCA (low byte)
Address:0x3C (BANK0)
Reset value:0x00
Bit
Bit name
7:0 IDLE_WAIT[7:0]
Reset value
0000_0000
R/W
Description
IDLE judgement max. wait time setting (low byte)
R/W
For details, please refer to [IDLE_WAIT_H:B0 0x3B] register
[Description]
1. For details operation of CCA, please refer to the “CCA(Clear Channel Asessment) function”.
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