ML7345 Datasheet, PDF (160/261 Pages) –

0x02[CLK_SET1]
Function: Clock setting 1
Address:0x02 (BANK0)
Reset value:0x1F
Bit
Bit name
7 CLK_INIT_DONE
6:5 Reserved
4 CLK4_EN
3 CLK3_EN
2 CLK2_EN
1 CLK1_EN
0 CLK0_EN
FEDL7345/D-02
ML7345/ML7345D
Reset value
0
00
1
1
1
1
1
R/W
Description
R
Clock stabilization completion flag
R/W
ADC clock control
R/W
0: clock stop
1: clock enable
RF function (RFstate control) clock control
R/W
0: clock stop
1: clock enable
TX function (MOD) clock control
R/W
0: clock stop
1: clock enable
RX function(DEMOD) clock control
R/W
0: clock stop
1: clock enable
PHY function clock control
R/W
0: clock stop
1: clock enable
0x03[CLK_SET2]
Function: Clock setting 2
Address: 0x03 (BANK0)
Reset value: 0x9B
Bit
Bit name
7 MSTR_CLK_EN
6 TCXO_EN
5 Reserved
4 XTAL_EN
3 RC32K_EN
2 Reserved
1 REG_PA_ENB
0 LOW_RATE_EN
Reset value
1
0
0
1
1
0
1
1
R/W
Description
Logic block clock enable control
R/W
0: disable
1: enable
TCXO input control (1) (2) (3)
R/W
0: disable
1: enable
R/W
Crystal oscillator circuits control (1) (2)
R/W
0: disable
1: enable
Internal RC oscillator control
R/W
0: disable
1: enable
R/W
PA regulator control
R/W
0: always-on
1: off at RX
Receiver section clock slowdown setting
0: disable
R/W
1: enable
* When this is set to 0b1, the current value for RX state described in the
“Power Consumption” is achieved.
(Note)
(1) In case of using TCXO, set TCXO_EN = 0b1. Please make sure only one of the register TCXO_EN and XTAL_EN_EN
is set to 0b1.
(2) RST0([RST_SET: B0 0x01(0)]) cannot clear this bit. In order to clear it, use the hardware reset (RESETN pin = “L”) or
set this bit to 0b0 by SPI access.
(3) In case of using TCXO, this register must be programmed first. If other registers are set before programming this register,
values set to other registers are not valid.
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