IS66WV1M16EALL Datasheet, PDF (9/15 Pages) Integrated Silicon Solution, Inc – ULTRA LOW POWER PSEUDO CMOS STATIC RAM

IS66WV1M16EALL
IS66/67WV1M16EBLL
WRITE CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol
Parameter
-55
Min Max
-70
Min Max
Unit Notes
t_WC
Write Cycle Time
55
-
70
-
ns
t_SCS1/SCS2 CS1#/CS2 to Write End
45
-
60
-
ns
t_CSM
Maximum CS1#/CS2 pulse width -
15
-
15
us
t_AW
Address Setup to Write Time
45
-
60
-
ns
t_HA
Address Hold to End of Write
0
-
0
-
ns
t_SA
Address Setup Time
0
-
0
-
ns
t_PWB
UB#/LB# Valid to End of Write
45
-
60
-
ns
t_PWE
WE# Pulse Width
45
-
60
-
ns
t_SD
Data Setup Time
25
-
30
-
ns
t_HZWE
UB#/LB# to High-Z output
0
-
0
-
ns
3
t_LZWE
UB#/LB# to Low-Z output
-
20
-
30
ns
3
t_CPH
CS1# HIGH (CS2 LOW) time
5
-
5
-
ns
Notes:
1. Test conditions and output loading are specified in the AC Test Conditions and AC Test Loads (Figure 1) on page 5.
2. The internal write time is defined by the overlap of CS1#, UB#, LB# and WE# LOW, CS2 HIGH . All signals must be
in valid states to initiate a Write, but anyone can go inactive to terminate Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signals that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested.
4. tPWE > tHzWE + tSD when OE# is LOW.
5. Chip Select Active Time (both CS1# LOW and CS2 HIGH) must not be longer than tCMS of 15 us.
Rev. 0A | October 2014
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