IS66WV1M16EALL Datasheet, PDF (7/15 Pages) Integrated Silicon Solution, Inc – ULTRA LOW POWER PSEUDO CMOS STATIC RAM

IS66WV1M16EALL
IS66/67WV1M16EBLL
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol
Parameter
-55
Min Max
-70
Min Max
Unit Notes
t_RC
Read cycle time
t_AA
Address Acess Time
55
-
70
-
ns
-
55
-
70
ns
1
t_OHA
Output Hold Time
10
-
10
-
ns
t_ACS1/ACS2 CS1#/CS2 Acess Time
-
55
-
70
ns
t_DOE
OE# Access Time
-
25
-
35
ns
1
t_HZOE
OE# to High-Z output
-
20
-
25
ns
2
t_LZOE
OE# to Low-Z output
5
-
5
-
ns
2
t_CSM
Maximum CS1#/CS2 pulse width -
15
-
15
us
t_HZCS1/HZCS2 CS1#/CS2 to High-Z output
0
20
0
25
ns
2
t_LZCS1/HZCS2 CS1#/CS2 to Low-Z output
10
-
10
-
ns
2
t_BA
UB#/LB# Acess Time
-
55
-
70
ns
1
t_HZB
UB#/LB# to High-Z output
0
20
0
25
ns
2
t_LZB
UB#/LB# to Low-Z output
0
-
0
-
ns
2
t_CPH
CS1# HIGH (CS2 LOW) time
5
-
5
-
ns
Notes:
1. Test conditions and output loading are specified in the AC Test Conditions and AC Test Loads (Figure 1) on page 5.
2. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1⁽¹⁾ (Address Controlled, OE#= VIL, WE#=VIH, UB# or LB# = VIL)
Address
CS1#
tRC
tCSM
CS2
tAA
tOHA
DQ 0-15 PREVIOUS DATA VALID
tOHA
DATA VALID
Notes:
1. WE# is HIGH for a Read Cycle.
Rev. 0A | October 2014
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