IS62WV12816DALL Datasheet, PDF (9/17 Pages) Integrated Silicon Solution, Inc – 128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
35 ns
Symbol Parameter Min. Max.
twc
Write Cycle Time
35 —
tscs1/tscs2 CS1/CS2 to Write End
25 —
taw
Address Setup Time to Write End
25
—
tha
Address Hold from Write End
0
—
tsa
Address Setup Time
0
—
tpwb
LB, UB Valid to End of Write
30 —
tpwe
WE Pulse Width
30 —
tsd
Data Setup to Write End
15 —
thd
Data Hold from Write End
0
—
thzwe⁽³⁾ WE LOW to High-Z Output
— 20
tlzwe⁽³⁾ WE HIGH to Low-Z Output
5
—
45 ns
55 ns
Min. Max. Min. Max. Unit
45 —
55 —
ns
35 —
45 —
ns
35 —
45 —
ns
0
—
0 —
ns
0
—
0 —
ns
35 —
45 —
ns
35 —
40 —
ns
20 —
25 —
ns
0
—
0 —
­ns
— 20
— 20
ns
5
—
5 —
ns
Notes:
1.  Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
9
Rev.  A
08/16/2011